Volume 1 Basic Architecture (794100), страница 97
Текст из файла (страница 97)
1ORPS instruction, 10-13OSXMMEXCPT flagcontrol register CR4, 11-25OUT instruction, 5-8, 7-28, 13-4OUTS instruction, 5-8, 7-28, 13-4Overflow exception (#OF), 6-18Overflow, x87 FPU stack, 8-36, 8-37PP6 family microarchitecturedescription of, 2-7history of, 2-3P6 family processorsdescription of, 1-1history of, 2-3P6 family microarchitecture, 2-7PABSB instruction, 5-28, 12-11PABSD instruction, 12-11PABSW instruction, 5-28, 12-11PackedBCD integer indefinite, 4-13BCD integers, 4-12bytes, 9-3doublewords, 9-3SIMD data types, 4-9SIMD floating-point values, 4-10SIMD integers, 4-10words, 9-3PACKSSWB instruction, 9-9PACKUSWB instruction, 9-9PADDB instruction, 9-8PADDD instruction, 9-8PADDQ instruction, 11-15PADDSB instruction, 9-8PADDSW instruction, 9-8PADDUSB instruction, 9-8PADDUSW instruction, 9-8PADDW instruction, 9-8PALIGNR instruction, 5-29, 12-12PAND instruction, 9-10PANDN instruction, 9-10Parameter passingargument list, 6-8on stack, 6-7on the stack, 6-7through general-purpose registers, 6-7x87 FPU register stack, 8-5XMM registers, 11-34PAUSE instruction, 11-18PAVGB instruction, 10-16PC (precision) field, x87 FPU control word, 8-11PCMPEQB instruction, 9-9PCMPEQD instruction, 9-9PCMPEQW instruction, 9-9PCMPGTB instruction, 9-9PCMPGTD instruction, 9-9PCMPGTW instruction, 9-9INDEXPE (inexact result exception) flag, 11-23MXCSR register, 4-23x87 FPU status word, 4-23, 8-7, 8-43Pentium 4 processor, 1-1description of, 2-4, 2-5Pentium 4 processor supporting Hyper-ThreadingTechnologydescription of, 2-4, 2-5Pentium II processor, 1-2description of, 2-3P6 family microarchitecture, 2-7Pentium II Xeon processordescription of, 2-3Pentium III processor, 1-2description of, 2-4P6 family microarchitecture, 2-7Pentium III Xeon processordescription of, 2-4Pentium M processordescription of, 2-5instructions supported, 2-5Pentium Pro processor, 1-2description of, 2-3P6 family microarchitecture, 2-7Pentium processor, 1-1history of, 2-2Pentium processor Extreme Editionintroduction, 2-5Pentium processor with MMX technology, 2-3Performance monitoring counters, 3-5PEXTRW instruction, 10-17PF (parity) flag, EFLAGS register, 3-21, A-1PHADDD instruction, 5-28, 12-10PHADDSW instruction, 5-28, 12-10PHADDW instruction, 5-28, 12-10PHSUBD instruction, 5-28, 12-10PHSUBSW instruction, 5-28, 12-10PHSUBW instruction, 5-28, 12-10Physicaladdress space, 3-8memory, 3-8PINSRW instruction, 10-17Pi, x87 FPU constant, 8-30PM (inexact result exception) mask bitMXCSR register, 11-23x87 FPU control word, 8-11, 8-43PMADDUBSW instruction, 5-28, 12-11PMADDWD instruction, 9-9PMAXSW instruction, 10-17PMAXUB instruction, 10-17PMINSW instruction, 10-17PMINUB instruction, 10-17PMOVMSKB instruction, 10-17PMULHRSW instruction, 5-29, 12-11PMULHUW instruction, 10-17PMULUDQ instruction, 11-15Pointer data types, 4-8Pointers64-bit mode, 4-8far pointer, 4-8near pointer, 4-8POP instruction, 6-1, 6-3, 7-8, 7-31POPA instruction, 6-8, 7-9POPF instruction, 3-20, 6-8, 7-30, 13-5POPFD instruction, 3-20, 6-8, 7-30POR instruction, 9-10Power coordination, 2-6PREFETCHh instructions, 10-19, 11-36Privilege levelsdescription of, 6-9inter-privilege level calls, 6-8protection rings, 6-9stack switching, 6-15Procedure callsdescription of, 6-5far call, 6-5for block-structured languages, 6-19inter-privilege level call, 6-10linking, 6-4near call, 6-5overview, 6-1return instruction pointer (EIP register), 6-4saving procedure state information, 6-8stack, 6-1stack switching, 6-10to exception handler procedure, 6-14to exception task, 6-17to interrupt handler procedure, 6-14to interrupt task, 6-17to other privilege levels, 6-8types of, 6-1Processor identificationearlier Intel architecture processors, 14-2early processors, 14-2notes on where to start, 14-1using CPUID, 14-1using CPUID instruction, 14-1Processor state information, saving, 6-8Protected modeI/O, 13-4memory models used, 3-10overview, 3-1Protection rings, 6-9PSADBW instruction, 10-17PSHUFB instruction, 5-29, 12-12PSHUFD instruction, 11-16PSHUFHW instruction, 11-15PSHUFLW instruction, 11-15PSHUFW instruction, 10-17, 11-16PSIGNB/W/D instruction, 5-29, 12-12PSLLD instruction, 9-10PSLLDQ instruction, 11-16PSLLQ instruction, 9-10PSLLW instruction, 9-10PSRLDQ instruction, 11-16PSUBB instruction, 9-8Vol.
1 INDEX-11INDEXPSUBD instruction, 9-8PSUBQ instruction, 11-15PSUBSB instruction, 9-8PSUBSW instruction, 9-8PSUBUSB instruction, 9-8PSUBUSW instruction, 9-8PSUBW instruction, 9-8PUNPCKHBW instruction, 9-9PUNPCKHDQ instruction, 9-9PUNPCKHQDQ instruction, 11-16PUNPCKHWD instruction, 9-9PUNPCKLBW instruction, 9-9PUNPCKLDQ instruction, 9-9PUNPCKLQDQ instruction, 11-16PUNPCKLWD instruction, 9-9PUSH instruction, 6-1, 6-3, 7-7, 7-31PUSHA instruction, 6-8, 7-8PUSHF instruction, 3-20, 6-8, 7-30PUSHFD instruction, 3-20, 6-8, 7-30PXOR instruction, 9-10QQNaN floating-point indefinite, 4-6, 4-20, 4-22, 8-20QNaNsdescription of, 4-20effect on COMISD and UCOMISD, 11-10encodings, 4-6operating on, 4-20rules for generating, 4-21using in applications, 4-21Quadword, 4-1, 9-3Quiet NaN (see QNaN)RR8D-R15D registers, 3-16R8-R15 registers, 3-16RAX register, 3-16RBP register, 3-16, 6-5RBX register, 3-16RC (rounding control) fieldMXCSR register, 4-23, 10-7x87 FPU control word, 4-23, 8-12RCL instruction, 7-19RCPPS instruction, 10-12RCPSS instruction, 10-12RCR instruction, 7-19RCX register, 3-16RDI register, 3-16RDX register, 3-16Real address modehandling exceptions in, 6-17handling interrupts in, 6-17memory model, 3-9, 3-10memory model used, 3-11not in 64-bit mode, 3-11overview, 3-1INDEX-12 Vol.
1Real numberscontinuum, 4-14encoding, 4-16, 4-17notation, 4-15system, 4-13Register operands64-bit mode, 3-28legacy modes, 3-27Register stack, x87 FPU, 8-2Registers64-bit mode, 3-16, 3-20control registers, 3-5CR in 64-bit mode, 3-6debug registers, 3-5EFLAGS register, 3-14, 3-20EIP register, 3-14, 3-24general purpose registers, 3-13, 3-14instruction pointer, 3-14machine check registers, 3-5memory management registers, 3-5MMX registers, 3-3, 9-3MSRs, 3-5MTRRs, 3-5MXCSR register, 10-6performance monitoring counters, 3-5REX prefix, 3-16segment registers, 3-13, 3-17x87 FPU registers, 8-1XMM registers, 3-3, 10-4Related literature, 1-9REP/REPE/REPZ/REPNE/REPNZprefixes, 7-27, 13-4Reserved bits, 1-5RESET pin, 3-20RET instruction, 3-24, 6-4, 6-5, 7-22, 7-32Return instruction pointer, 6-4Returns, from procedure callsexception handler, return from, 6-14far return, 6-6inter-privilege level return, 6-10interrupt handler, return from, 6-14near return, 6-5REX prefixes, 3-2, 3-16, 3-25RF (resume) flag, EFLAGS register, 3-23, A-1RFLAGS, 3-24RFLAGS register, 7-31See EFLAGS registerRIP register, 6-564-bit mode, 7-2description of, 3-24relation to EIP, 7-2ROL instruction, 7-19ROR instruction, 7-19Roundingmodes, floating-point operations, 4-23modes, x87 FPU, 8-12toward zero (truncation), 4-24Rounding control (RC) fieldINDEXMXCSR register, 4-23, 10-7x87 FPU control word, 4-23, 8-12RSI register, 3-16RSP register, 3-16, 6-5RSQRTPS instruction, 10-12RSQRTSS instruction, 10-12SSAHF instruction, 3-20, 7-30SAL instruction, 7-15SAR instruction, 7-17Saturation arithmetic (MMX instructions), 9-5SBB instruction, 7-12Scalar operationsdefined, 10-10, 11-7scalar double-precision FP operands, 11-7scalar single-precision FP operands, 10-10Scale (operand addressing), 3-30, 3-32Scale, x87 FPU operation, 8-31Scaling bias value, 8-41, 8-42SCAS instruction, 3-22, 7-27Segmentdefined, 3-8maximum number, 3-8Segment override prefixes, 3-29Segment registers64-bit mode, 3-20, 3-30, 7-2default usage rules, 3-29description of, 3-13, 3-17part of basic programming environment, 7-1Segment selectordescription of, 3-8, 3-17segment override prefixes, 3-29specifying, 3-29Segmented memory model, 1-6, 3-8, 3-18Serialization of I/O instructions, 13-7Serializing instructions, 13-7SETcc instructions, 3-22, 7-20SF (sign) flag, EFLAGS register, 3-21, A-1SF (stack fault) flag, x87 FPU status word, 8-9, 8-37SFENCE instruction, 10-20, 11-17, 11-37SHL instruction, 7-15SHLD instruction, 7-18SHR instruction, 7-16SHRD instruction, 7-18Shuffle instructionsSSE extensions, 10-14SSE2 extensions, 11-10SHUFPD instruction, 11-10SI register, 3-16Signaling NaN (see SNaN)Signedinfinity, 4-19integers, description of, 4-4integers, encodings, 4-5zero, 4-18Significand, of floating-point number, 4-14Sign, floating-point number, 4-14SIMD floating-point exception (#XM), 11-25SIMD floating-point exceptionsdenormal operand exception (#D), 11-21divide-by-zero (#Z), 11-22exception conditions, 11-19exception handlers, E-1inexact result exception (#P), 11-23invalid operation exception (#I), 11-20list of, 11-19numeric overflow exception (#O), 11-22numeric underflow exception (#U), 11-22precision exception (#P), 11-23software handling, 11-26summary of, C-1writing exception handlers for, E-1SIMD floating-point flag bits, 10-6SIMD floating-point mask bits, 10-6SIMD floating-point rounding control field, 10-7SIMD (single-instruction, multiple-data)execution model, 2-3, 2-4, 9-4instructions, 2-15, 5-20, 10-10MMX instructions, 5-14operations, on packed double-precisionfloating-point operands, 11-6operations, on packed single-precisionfloating-point operands, 10-9packed data types, 4-9SSE instructions, 5-16SSE2 instructions, 11-6, 12-3, 12-9Sine, x87 FPU operation, 8-29Single-precision floating-point format, 4-5Sleep, 2-6Smart cache, 2-6Smart memory access, 2-13smart memory access, 2-6SMMmemory model used, 3-11overview, 3-1SNaNsdescription of, 4-20effect on COMISD and UCOMISD, 11-10encodings, 4-6operating on, 4-20typical uses of, 4-20using in applications, 4-21Software compatibility, 1-5SP register, 3-16Speculative execution, 2-7, 2-10Spin-wait loopsprogramming with PAUSE instruction, 11-18SQRTPD instruction, 11-8SQRTPS instruction, 10-12SQRTSD instruction, 11-9SQRTSS instruction, 10-12SS register, 3-17, 3-19, 6-1SSE extensions128-bit packed single-precision data type, 10-8Vol.
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