Volume 1 Basic Architecture (794100), страница 95
Текст из файла (страница 95)
1 INDEX-1INDEXADDPD instruction, 11-8ADDPS instruction, 10-12Address size attributecode segment, 3-24description of, 3-24of stack, 6-3Address sizes, 3-11Address space64-bit mode, 3-2, 3-6compatibility mode, 3-2overview of, 3-3physical, 3-8Addressing modesassembler, 3-32base, 3-30, 3-31, 3-32base plus displacement, 3-31base plus index plus displacement, 3-32base plus index time scale plus displacement, 3-32canonical address, 3-13displacement, 3-30, 3-31, 3-32effective address, 3-30immediate operands, 3-26index, 3-30, 3-32index times scale plus displacement, 3-32memory operands, 3-28register operands, 3-27, 3-28RIP-relative addressing, 3-24, 3-32scale factor, 3-30, 3-32specifying a segment selector, 3-29specifying an offset, 3-30specifying offsets in 64-bit mode, 3-32ADDSD instruction, 11-8ADDSS instruction, 10-12ADDSUBPD instruction, 5-26, 12-5ADDSUBPS instruction, 5-26, 12-5Advanced media boost, 2-13advanced smart cache, 2-13AF (adjust) flag, EFLAGS register, 3-21, A-1AH register, 3-16AL register, 3-16Alignmentwords, doublewords, quadwords, 4-2AND instruction, 7-15ANDNPD instruction, 11-9ANDNPS instruction, 10-13ANDPD instruction, 11-9ANDPS instruction, 10-13Arctangent, x87 FPU operation, 8-29Arithmetic instructions, x87 FPU, 8-35Assembler, addressing modes, 3-32Asymmetric processing model, 12-2AX register, 3-16BB (default size) flag, segment descriptor, 3-24Base (operand addressing), 3-30, 3-31, 3-32Basic execution environment, 3-2INDEX-2 Vol.
1Basic programming environment, 7-1, 7-2B-bit, x87 FPU status word, 8-7BCD integerspacked, 4-12relationship to status flags, 3-22unpacked, 4-12, 7-14x87 FPU encoding, 4-12, 4-13BH register, 3-16Bias valuenumeric overflow, 8-41numeric underflow, 8-42Biased exponent, 4-16Biasing constant, for floating-point numbers, 4-7Binary numbers, 1-6Binary-coded decimal (see BCD)Bit field, 4-9Bit order, 1-4BL register, 3-16BOUND instruction, 6-18, 7-26, 7-32BOUND range exceeded exception (#BR), 6-18BP register, 3-16Branchcontrol transfer instructions, 7-21hints, 11-18on EFLAGS register status flags, 7-23, 8-9on x87 FPU condition codes, 8-9, 8-28prediction, 2-8BSF instruction, 7-20BSR instruction, 7-20BSWAP instruction, 7-5BT instruction, 3-20, 3-22, 7-20BTC instruction, 3-20, 3-22, 7-20BTR instruction, 3-20, 3-22, 7-20BTS instruction, 3-20, 3-22, 7-20BX register, 3-16Byte, 4-1Byte order, 1-4CC1 flag, x87 FPU status word, 8-7, 8-37, 8-41, 8-43C2 flag, x87 FPU status word, 8-7cache, smart, 2-6Call gate, 6-9CALL instruction, 3-24, 6-4, 6-5, 6-9, 7-22, 7-32Calls (see Procedure calls)Canonical address, 3-13CBW instruction, 7-11CDQ instruction, 7-11Celeron processordescription of, 2-3CF (carry) flag, EFLAGS register, 3-21, A-1CH register, 3-16CL register, 3-16CLC instruction, 3-22, 7-29CLD instruction, 3-22, 7-30CLFLUSH instruction, 11-17CLI instruction, 13-5INDEXCMC instruction, 3-22, 7-29CMOVcc instructions, 7-4, 7-6CMP instruction, 7-12CMPPD instruction, 11-10CMPPS instruction, 10-13CMPS instruction, 3-22, 7-27CMPSD instruction, 11-10CMPSS instruction, 10-14CMPXCHG instruction, 7-6CMPXCHG16B instruction, 7-7CMPXCHG8B instruction, 7-6Code segment, 3-19COMISD instruction, 11-10COMISS instruction, 10-14Comparecompare and exchange, 7-6integers, 7-12real numbers, x87 FPU, 8-27strings, 7-27Compatibility modeaddress space, 3-2branch functions, 6-12call gate descriptors, 6-12introduction, 2-21, 3-2memory models, 3-11MMX technology, 9-2segmentation, 3-30SSE extensions, 10-4SSE2 extensions, 11-4SSE3 extensions, 12-1SSSE3 extensions, 12-1x87 FPU, 8-2See also: IA-32e mode, 64-bit modeCompatibility, software, 1-5compilersdocumentation, 1-9Condition code flags, x87 FPU status wordbranching on, 8-9conditional moves on, 8-9description of, 8-6interpretation of, 8-8use of, 8-27Conditional moves, x87 FPU condition codes, 8-9Constants (floating point), 8-24Control registers64-bit mode, 3-6overview of, 3-5Core microarchitecture, 2-12core microarchitecture, 2-12Core Solo and Core Duo, 2-5Cosine, x87 FPU operation, 8-29CPUID instructionAP-485, 1-9CLFLUSH flag, 11-17CMOVcc feature flag, 7-5determine support for, 3-23earlier processors, 14-2FXSAVE-FXRSTOR flag, 10-21MMX feature flag, 9-11processor identification, 14-1serializing use, 13-7SSE feature flag, 10-1, 10-9SSE2 feature flag, 11-1, 12-7, 12-8SSE3 feature flag, 12-8SSSE2 feature flag, 12-13summary of, 7-33CS register, 3-17, 3-19CTI instruction, 7-31Current privilege level (see CPL)Current stack, 6-2, 6-4CVTDQ2PD instruction, 11-14CVTDQ2PS instruction, 11-14CVTPD2DQ instruction, 11-14CVTPD2PI instruction, 11-13CVTPD2PS instruction, 11-12CVTPI2PD instruction, 11-13CVTPI2PS instruction, 10-16CVTPS2DQ instruction, 11-14CVTPS2PD instruction, 11-12CVTPS2PI instruction, 10-16CVTSD2SI instruction, 11-14CVTSD2SS instruction, 11-12CVTSI2SD instruction, 11-14CVTSI2SS instruction, 10-16CVTSS2SD instruction, 11-12CVTSS2SI instruction, 10-16CVTTPD2DQ instruction, 11-14CVTTPD2PI instruction, 11-13CVTTPS2DQ instruction, 11-14CVTTPS2PI instruction, 10-16CVTTSD2SI instruction, 11-14CVTTSS2SI instruction, 10-16CWD instruction, 7-11CWDE instruction, 7-11CX register, 3-16DD (default size) flag, segment descriptor, 6-3DAA instruction, 7-14DAS instruction, 7-14Data movement instructions, 7-3Data pointer, x87 FPU, 8-13Data registers, x87 FPU, 8-2Data segment, 3-19Data types128-bit packed SIMD, 4-1064-bit mode, 7-264-bit packed SIMD, 4-10alignment, 4-2BCD integers, 4-12, 7-14bit field, 4-9byte, 4-1doubleword, 4-1floating-point, 4-5fundamental, 4-1Vol.
1 INDEX-3INDEXintegers, 4-4numeric, 4-3operated on by GP instructions, 7-1, 7-2operated on by MMX technology, 9-3operated on by SSE extensions, 10-8operated on by SSE2 extensions, 11-5operated on by x87 FPU, 8-17operated on in 64-bit mode, 4-8packed bytes, 9-3packed doublewords, 9-3packed SIMD, 4-9packed words, 9-3pointers, 4-8quadword, 4-1, 9-3signed integers, 4-4strings, 4-9unsigned integers, 4-4word, 4-1DAZ (denormals-are-zeros) flagMXCSR register, 10-7DE (denormal operand exception) flagMXCSR register, 11-21x87 FPU status word, 8-7, 8-39Debug registers64-bit mode, 3-6legacy modes, 3-5DEC instruction, 7-12Decimal integers, x87 FPU, 4-13Deeper sleep, 2-6Denormal number (see Denormalized finite number)Denormal operand exception (#D)overview of, 4-26SSE and SSE2 extensions, 11-21x87 FPU, 8-38Denormalization process, 4-19Denormalized finite number, 4-6, 4-18Denormals-are-zeroDAZ flag, MXCSR register, 10-7, 11-3, 11-4,11-28mode, 10-7, 11-28DF (direction) flag, EFLAGS register, 3-22, A-1DH register, 3-16DI register, 3-16Digital media boost, 2-6Displacement (operand addressing), 3-30, 3-31, 3-32DIV instruction, 7-13Divide, 4-27Divide by zero exception (#Z)SSE and SSE2 extensions, 11-22x87 FPU, 8-40DIVPD instruction, 11-8DIVPS instruction, 10-12DIVSD instruction, 11-8DIVSS instruction, 10-12DL register, 3-16DM (denormal operand exception) mask bitMXCSR register, 11-21x87 FPU, 8-39INDEX-4 Vol.
1x87 FPU control word, 8-11Double-extended-precision FP format, 4-5Double-precision floating-point format, 4-5Doubleword, 4-1DS register, 3-17, 3-19Dual-core technologyintroduction, 2-19DX register, 3-16Dynamic data flow analysis, 2-8Dynamic execution, 2-8, 2-13EEAX register, 3-14, 3-16EBP register, 3-14, 3-16, 6-4, 6-8EBX register, 3-14, 3-16ECX register, 3-14, 3-16EDI register, 3-14, 3-16EDX register, 3-14, 3-16Effective address, 3-30EFLAGS register64-bit mode, 7-2condition codes, B-1cross-reference with instructions, A-1description of, 3-20instructions that operate on, 7-29overview, 3-14part of basic programming environment, 7-1restoring from stack, 6-8saving on a procedure call, 6-8status flags, 8-9, 8-10, 8-28use with CMOVcc instructions, 7-4EIP registerdescription of, 3-24overview, 3-14part of basic programming environment, 7-1relationship to CS register, 3-19EMMS instruction, 9-10, 9-12Enhanced Intel Deeper Sleep, 2-6ENTER instruction, 6-19, 6-20, 7-29ES register, 3-17, 3-19ES (exception summary) flagx87 FPU status word, 8-44ESC instructions, x87 FPU, 8-22ESI register, 3-14, 3-16ESP register, 3-16ESP register (stack pointer), 3-14, 6-3, 6-4Exception flags, x87 FPU status word, 8-7Exception handlersoverview of, 6-13SIMD floating-point exceptions, E-1SSE and SSE2 extensions, 11-25, 11-26typical actions of a FP exception handler, 4-31x87 FPU, 8-45Exception priority, floating-point exceptions, 4-30Exception-flag masks, x87 FPU control word, 8-11Exceptions64-bit mode, 6-19INDEXdescription of, 6-13handler, 6-13implicit call to handler, 6-1in real-address mode, 6-17notation, 1-8vector, 6-13Exponent, floating-point number, 4-14FF2XM1 instruction, 8-31FABS instruction, 8-25FADD instruction, 8-25FADDP instruction, 8-25Far calldescription of, 6-5operation, 6-6Far pointer16-bit addressing, 3-1132-bit addressing, 3-1164-bit mode, 4-8description of, 3-8, 4-8legacy modes, 4-8Far return operation, 6-6FBLD instruction, 8-23FBSTP instruction, 8-23FCHS instruction, 8-25FCLEX/FNCLEX instructions, 8-7FCMOVcc instructions, 8-10, 8-23FCOM instruction, 8-9, 8-26FCOMI instruction, 8-10, 8-26FCOMIP instruction, 8-10, 8-26FCOMP instruction, 8-9, 8-26FCOMPP instruction, 8-9, 8-26FCOS instruction, 8-7, 8-29FDIV instruction, 8-25FDIVP instruction, 8-25FDIVR instruction, 8-25FDIVRP instruction, 8-25Feature determination, of processor, 14-1FIADD instruction, 8-25FICOM instruction, 8-9, 8-26FICOMP instruction, 8-9, 8-26FIDIV instruction, 8-25FIDIVR instruction, 8-25FILD instruction, 8-23FIMUL instruction, 8-25FINIT/FNINIT instructions, 8-7, 8-11, 8-12, 8-32FIST instruction, 8-23FISTP instruction, 8-23FISTTP instruction, 5-25, 12-4FISUB instruction, 8-25FISUBR instruction, 8-25Flagscross-reference with instructions, A-1Flat memory model, 3-8, 3-18FLD instruction, 8-22FLD1 instruction, 8-24FLDCW instruction, 8-10, 8-32FLDENV instruction, 8-7, 8-13, 8-15, 8-33FLDL2E instruction, 8-24FLDL2T instruction, 8-24FLDLG2 instruction, 8-24FLDLN2 instruction, 8-24FLDPI instruction, 8-24FLDSW instruction, 8-32FLDZ instruction, 8-24Floating-point data typesbiasing constant, 4-7denormalized finite number, 4-6description of, 4-5double extended precision format, 4-5, 4-6double precision format, 4-5, 4-6infinites, 4-6normalized finite number, 4-6single precision format, 4-5, 4-6SSE extensions, 10-8SSE2 extensions, 11-5storing in memory, 4-7x87 FPU, 8-17zeros, 4-6Floating-point exception handlersSSE and SSE2 extensions, 11-25, 11-26typical actions, 4-31x87 FPU, 8-45Floating-point exceptionsdenormal operand exception (#D), 4-26, 8-39,11-21, C-1divide by zero exception (#Z), 4-27, 8-40, 11-22,C-1exception conditions, 4-26exception priority, 4-30inexact result (precision) exception (#P), 4-29,8-42, 11-22, C-1invalid operation exception (#I), 4-26, 8-36, 11-20invalid-operation exception (#IA), C-1invalid-operation exception (#IS), C-1invalid-operation exception (#I), C-1numeric overflow exception (#O), 4-27, 8-40,11-22, C-1numeric underflow exception (#U), 4-28, 8-41,11-22, C-1summary of, 4-24, C-1typical handler actions, 4-31Floating-point formatbiased exponent, 4-16description of, 8-17exponent, 4-14fraction, 4-14indefinite, 4-6QNaN floating-point indefinite, 4-22real number system, 4-13sign, 4-14significand, 4-14Floating-point numbersdefined, 4-14Vol.
1 INDEX-5INDEXencoding, 4-6Flush-to-zeroFZ flag, MXCSR register, 10-7, 11-3mode, 10-7FMUL instruction, 8-25FMULP instruction, 8-25FNOP instruction, 8-32Fopcode compatibility mode, 8-14FPATAN instruction, 8-29FPREM instruction, 8-7, 8-25, 8-30FPREM1 instruction, 8-7, 8-25, 8-30FPTAN instruction, 8-7Fraction, floating-point number, 4-14FRNDINT instruction, 8-25FRSTOR instruction, 8-7, 8-13, 8-15, 8-33FS register, 3-17, 3-19FSAVE/FNSAVE instructions, 8-6, 8-7, 8-13, 8-15,8-33FSCALE instruction, 8-31FSIN instruction, 8-7, 8-29FSINCOS instruction, 8-7, 8-29FSQRT instruction, 8-25FST instruction, 8-23FSTCW/FNSTCW instructions, 8-10, 8-32FSTENV/FNSTENV instructions, 8-6, 8-13, 8-15, 8-33FSTP instruction, 8-23FSTSW/FNSTSW instructions, 8-6, 8-32FSUB instruction, 8-25FSUBP instruction, 8-25FSUBR instruction, 8-25FSUBRP instruction, 8-25FTST instruction, 8-9, 8-26FUCOM instruction, 8-26FUCOMI instruction, 8-10, 8-26FUCOMIP instruction, 8-10, 8-26FUCOMP instruction, 8-26FUCOMPP instruction, 8-9, 8-26FXAM instruction, 8-7, 8-26FXCH instruction, 8-23FXRSTOR instruction, 5-13, 8-17, 10-20, 11-34FXSAVE instruction, 5-13, 8-17, 10-20, 11-34FXTRACT instruction, 8-25FYL2X instruction, 8-31FYL2XP1 instruction, 8-31GGDTR register, 3-5, 3-6General purpose registers64-bit mode, 3-6, 3-17description of, 3-13, 3-14overview of, 3-3, 3-6parameter passing, 6-7part of basic programming environment, 7-1, 7-2using REX prefix, 3-17General-purpose instructions64-bit mode, 7-2basic programming environment, 7-1INDEX-6 Vol.
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