Volume 1 Basic Architecture (794100), страница 96
Текст из файла (страница 96)
1data types operated on, 7-1, 7-2description of, 7-1origin of, 7-1programming with, 7-1summary of, 5-2, 7-3GS register, 3-17, 3-19HHADDPD instruction, 5-26, 12-6HADDPS instruction, 5-26, 12-5Hexadecimal numbers, 1-6Horizontal processing model, 12-2HSUBPD instruction, 5-26, 12-6HSUBPS instruction, 5-26, 12-6HT Technologyfirst processor, 2-4implementing, 2-19introduction, 2-18IIA-32 architecturehistory of, 2-1introduction to, 2-1IA-32e modeintroduction, 2-21segmentation, 3-30See also: 64-bit mode, compatibility modeIA32_MISC_ENABLE MSR, 8-14ID (identification) flag, EFLAGS register, 3-23IDIV instruction, 7-13IDTR register, 3-5, 3-6IE (invalid operation exception) flagMXCSR register, 11-20x87 FPU status word, 8-7, 8-37, 8-38IEEE Standard 754, 4-5, 4-13, 8-1IF (interrupt enable) flagEFLAGS register, 3-23, 6-14, 13-5, A-1IM (invalid operation exception) mask bitMXCSR register, 11-20x87 FPU control word, 8-11Immediate operands, 3-26IMUL instruction, 7-13IN instruction, 5-8, 7-28, 13-4INC instruction, 7-12Indefinitedescription of, 4-22floating-point format, 4-6, 4-17integer, 4-5, 8-20packed BCD integer, 4-13QNaN floating-point, 4-20, 4-22Index (operand addressing), 3-30, 3-32Inexact result (precision)exception (#P), overview, 4-29exception (#P), SSE-SSE2 extensions, 11-23exception (#P), x87 FPU, 8-42on floating-point operations, 4-23INDEXInfinity control flag, x87 FPU control word, 8-12Infinity, floating-point format, 4-6, 4-19INIT pin, 3-20Input/output (see I/O)INS instruction, 5-8, 7-28, 13-4Instruction operands, 1-6Instruction pointer64-bit mode, 7-2EIP register, 3-14, 3-24RIP register, 3-24RIP, EIP, IP compared, 3-12x87 FPU, 8-13Instruction prefixeseffect on SSE and SSE2 instructions, 11-37REX prefix, 3-2, 3-16Instruction setbinary arithmetic instructions, 7-12bit scan instructions, 7-20bit test and modify instructions, 7-20byte-set-on-condition instructions, 7-20cacheability control instructions, 5-20, 5-24comparison and sign change instruction, 7-12control transfer instructions, 7-21data movement instructions, 7-3decimal arithmetic instructions, 7-13EFLAGS cross-reference, A-1EFLAGS instructions, 7-29exchange instructions, 7-5FXSAVE and FXRSTOR instructions, 5-13general-purpose instructions, 5-2grouped by processor, 5-1increment and decrement instructions, 7-12instruction ordering instructions, 5-20, 5-24I/O instructions, 5-8, 7-28logical instructions, 7-15MMX instructions, 5-14, 9-6multiply and divide instructions, 7-13processor identification instruction, 7-33repeating string operations, 7-27rotate instructions, 7-18segment register instructions, 7-31shift instructions, 7-15SIMD instructions, introduction to, 2-15software interrupt instructions, 7-25SSE instructions, 5-16SSE2 instructions, 5-20stack manipulation instructions, 7-7string operation instructions, 7-26summary, 5-1system instructions, 5-29test instruction, 7-21type conversion instructions, 7-10x87 FPU and SIMD state managementinstructions, 5-13x87 FPU instructions, 5-10INT instruction, 6-18, 7-32Integersdescription of, 4-4indefinite, 4-5, 8-20signed integer encodings, 4-5signed, description of, 4-4unsigned integer encodings, 4-4unsigned, description of, 4-4Intel 64 architecture64-bit mode, 3-264-bit mode instructions, 5-30address space, 3-8compatibility mode, 3-2data types, 4-1definition of, 1-2executing calls, 6-1general purpose instructions, 7-1generations, 2-22history of, 2-1IA32e mode, 3-2introduction, 2-21memory organization, 3-8, 3-10relation to IA-32, 1-2See also: IA-32e modeIntel Advanced Digital Media Boost, 2-6, 2-13Intel Advanced Smart Cache, 2-13Intel Advanced Thermal Manager, 2-6Intel Core 2 Extreme processor family, 2-6, 2-21Intel Core Duo processor, 2-5, 2-20Intel Core microarchitecture, 2-6, 2-12, 2-21Intel Core Solo processor, 2-5Intel developer link, 1-9Intel Dynamic Power Coordination, 2-6Intel NetBurst microarchitecture, 1-2description of, 2-9introduction, 2-9Intel Pentium D processor, 2-20Intel Pentium processor Extreme Edition, 2-19Intel Smart Cache, 2-6Intel Smart Memory Access, 2-6, 2-13Intel software network link, 1-9Intel VTune Performance Analyzerrelated information, 1-9Intel Wide Dynamic Execution, 2-6, 2-13Intel Xeon processor, 1-1description of, 2-4Intel Xeon processor 5100 series, 2-6, 2-21Intel386 processor, 2-2Intel486 processorhistory of, 2-2Inter-privilege level calldescription of, 6-8operation, 6-10Inter-privilege level returndescription of, 6-8operation, 6-10Interrupt gate, 6-14Interrupt handler, 6-13Interrupt vector, 6-13Interrupts64-bit mode, 6-19Vol.
1 INDEX-7INDEXdescription of, 6-13handler, 6-13implicit call to an interrupt handlerprocedure, 6-14implicit call to an interrupt handler task, 6-17implicit call to interrupt handler procedure, 6-14implicit call to interrupt handler task, 6-17in real-address mode, 6-17maskable, 6-13user-defined, 6-13vector, 6-13INTn instruction, 7-26INTO instruction, 6-18, 7-26, 7-32Invalid arithmetic operand exception (#IA)description of, 8-38masked response to, 8-38Invalid operation exception (#I)overview, 4-26SSE and SSE2 extensions, 11-20x87 FPU, 8-36IOPL (I/O privilege level) fieldEFLAGS register, 3-23, 13-4IRET instruction, 3-24, 6-17, 6-18, 7-22, 7-32, 13-5I/Oaddress space, 13-2instruction serialization, 13-7instructions, 5-8, 7-28, 13-3I/O privilege level (see IOPL)map base, 13-5permission bit map, 13-5ports, 3-5, 13-1, 13-2, 13-4, 13-7sensitive instructions, 13-4JJ-bit, 4-14Jcc instructions, 3-22, 3-24, 7-23JMP instruction, 3-24, 7-21, 7-32LL1 (level 1) cache, 2-7, 2-10L2 (level 2) cache, 2-7, 2-10LAHF instruction, 3-20, 7-30Last instruction opcode, x87 FPU, 8-14LDDQU instruction, 5-25, 12-4LDMXCSR instruction, 10-17, 11-34LDS instruction, 7-32LDTR register, 3-5, 3-6LEA instruction, 7-33LEAVE instruction, 6-19, 6-25, 7-29LES instruction, 7-32LFENCE instruction, 11-17LGS instruction, 7-32Linear address, 3-8Linear address spacedefined, 3-8maximum size, 3-8INDEX-8 Vol.
1LOCK signal, 7-5LODS instruction, 3-22, 7-27Log epsilon, x87 FPU operation, 8-31Logical address, 3-8LOOP instructions, 7-24LOOPcc instructions, 3-22, 7-24LSS instruction, 7-32MMachine check registers, 3-5Machine specific registers (see MSRs)Maskable interrupts, 6-13Masked responsesdenormal operand exception (#D), 4-26, 8-39divide by zero exception (#Z), 4-27, 8-40inexact result (precision) exception (#P), 4-30,8-43invalid arithmetic operation (#IA), 8-38invalid operation exception (#I), 4-26numeric overflow exception (#O), 4-28, 8-40numeric underflow exception (#U), 4-29, 8-42stack overflow or underflowexception (#IS), 8-37MASKMOVDQU instruction, 11-17, 11-36MASKMOVQ instruction, 10-18, 11-36Masks, exception-flagsMXCSR register, 10-6x87 FPU control word, 8-11MAXPD instruction, 11-9MAXPS instruction, 10-12MAXSD instruction, 11-9MAXSS instruction, 10-13Memoryflat memory model, 3-8management registers, 3-5memory type range registers (MTRRs), 3-5modes of operation, 3-10organization, 3-8physical, 3-8real address mode memory model, 3-9, 3-10segmented memory model, 3-8virtual-8086 mode memory model, 3-9, 3-10Memory operands64-bit mode, 3-28legacy modes, 3-28Memory-mapped I/O, 13-2MFENCE instruction, 11-17, 11-37Microarchitecture(see Intel NetBurst microarchitecture)(see P6 family microarchitecture)MINPD instruction, 11-9MINPS instruction, 10-13MINSD instruction, 11-9MINSS instruction, 10-13MMX instruction setarithmetic instructions, 9-8comparison instructions, 9-9INDEXconversion instructions, 9-9data transfer instructions, 9-8EMMS instruction, 9-10logical instructions, 9-10overview, 9-6shift instructions, 9-10MMX registersdescription of, 9-3overview of, 3-3MMX technology64-bit mode, 9-264-bit packed SIMD data types, 4-10compatibility mode, 9-2compatibility with FPU architecture, 9-10data types, 9-3detecting MMX technology with CPUIDinstruction, 9-11effect of instruction prefixes on MMXinstructions, 9-14exception handling in MMX code, 9-14IA-32e mode, 9-2instruction set, 5-14, 9-6interfacing with MMX code, 9-13introduction to, 9-1memory data formats, 9-4mixing MMX and floating-point instructions, 9-13MMX registers, 9-3programming environment (overview), 9-2register mapping, 9-14saturation arithmetic, 9-5SIMD execution environment, 9-4transitions between x87 FPU - MMX code, 9-12updating MMX technology routines using 128-bitSIMD integer instructions, 11-35using MMX code in a multitasking operatingsystem environment, 9-14using the EMMS instruction, 9-12wraparound mode, 9-5Modes of operation64-bit mode, 3-2compatibility mode, 3-2memory models used with, 3-10overview, 3-1, 3-6protected mode, 3-1real address mode, 3-1system management mode (SMM), 3-1MONITOR instruction, 5-27, 12-7Moore’s law, 2-22MOV instruction, 7-4, 7-31MOVAPD instruction, 11-7, 11-34MOVAPS instruction, 10-11, 11-34MOVD instruction, 9-8MOVDDUP instruction, 5-27, 12-5MOVDQ2Q instruction, 11-16MOVDQA instruction, 11-15, 11-34MOVDQU instruction, 11-15, 11-34MOVHLPS instruction, 10-11MOVHPD instruction, 11-8MOVHPS instruction, 10-11MOVLHPS instruction, 10-11MOVLPD instruction, 11-8MOVLPS instruction, 10-11MOVMSKPD instruction, 11-8MOVMSKPS instruction, 10-11MOVNTDQ instruction, 11-17, 11-36MOVNTI instruction, 11-17, 11-36MOVNTPD instruction, 11-17, 11-36MOVNTPS instruction, 10-18, 11-36MOVNTQ instruction, 10-18, 11-36MOVQ instruction, 9-8MOVQ2DQ instruction, 11-16MOVS instruction, 3-22, 7-27MOVSD instruction, 11-7, 11-34MOVSHDUP instruction, 5-26, 12-4MOVSLDUP instruction, 5-27, 12-4MOVSS instruction, 10-11, 11-34MOVSX instruction, 7-11MOVSXD instruction, 7-11MOVUPD instruction, 11-7, 11-34MOVUPS instruction, 10-9, 10-11, 11-34MOVZX instruction, 7-11MS-DOS compatibility mode, 8-45, D-1MSRs, 3-5MTRRs, 3-5MUL instruction, 7-13MULPD instruction, 11-8MULPS instruction, 10-12MULSD instruction, 11-8MULSS instruction, 10-12Multi-core technology, 2-19Multi-threading capability, 2-19MWAIT instruction, 5-27, 12-7MXCSR register, 11-23denormals-are-zero (DAZ) flag, 10-7, 11-3, 11-4description, 10-5flush-to-zero flag (FZ), 10-7FXSAVE and FXRSTOR instructions, 11-34LDMXCSR instruction, 11-34load and store instructions, 10-17RC field, 4-23saving on a procedure or function call, 11-34SIMD floating-point mask and flag bits, 10-6SIMD floating-point rounding control field, 10-7state management instructions, 5-19, 10-17STMXCSR instruction, 11-34writing to while preventing general-protectionexceptions (#GP), 11-30NNaNsdescription of, 4-17, 4-19encoding of, 4-6, 4-17SNaNs vs.
QNaNs, 4-19Near calldescription of, 6-5Vol. 1 INDEX-9INDEXoperation, 6-5Near pointer64-bit mode, 4-8legacy modes, 4-8Near return operation, 6-5NEG instruction, 7-12NetBurst microarchitecture(see Intel NetBurst microarchitecture)Non-arithmetic instructions, x87 FPU, 8-35Non-number encodings, floating-point format, 4-16Non-temporal datacaching of, 10-18description, 10-18temporal vs.
non-temporal data, 10-18Non-waiting instructions, x87 FPU, 8-33, 8-45NOP instruction, 7-33Normalized finite number, 4-6, 4-16, 4-18NOT instruction, 7-15Notationbit and byte order, 1-4exceptions, 1-8hexadecimal and binary numbers, 1-6instruction operands, 1-6notational conventions, 1-4reserved bits, 1-5segmented addressing, 1-6NT (nested task) flag, EFLAGS register, 3-23, A-1Numeric overflow exception (#O)overview, 4-27SSE and SSE2 extensions, 11-22x87 FPU, 8-7, 8-40Numeric underflow exception (#U)overview, 4-28SSE and SSE2 extensions, 11-22x87 FPU, 8-7, 8-41OOE (numeric overflow exception) flagMXCSR register, 11-22x87 FPU status word, 8-7, 8-40OF (overflow) flagEFLAGS register, 3-21, 6-18OF (overflow) flag, EFLAGS register, A-1Offset (operand addressing), 3-30Offset (operand addressing, 64-bit mode), 3-32OM (numeric overflow exception) mask bitMXCSR register, 11-22x87 FPU control word, 8-11, 8-40Operandaddressing, modes, 3-26instruction, 1-6size attribute, 3-24sizes, 3-11, 3-25x87 FPU instructions, 8-22OR instruction, 7-15Ordering I/O, 13-7ORPD instruction, 11-9INDEX-10 Vol.
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