Volume 1 Basic Architecture (794100), страница 92
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MAXPS, MAXSS, MINPS, MINSS, MAXPD, MAXSD, MINPD, MINSDSource OperandsMasked ResultUnmasked ResultOpd1 op NaN2 (any Opd1)NaN2NoneNaN1 op Opd2 (any Opd2)Opd2NoneNOTE:1. SNaN and QNaN operands raise an Invalid Operation fault.Table E-10. SQRTPS, SQRTSS, SQRTPD, SQRTSDSource OperandMasked ResultUnmasked ResultQNaNQNaNQNaN (not an exception)SNaNSNaN | 00400000H orSNaN |0008000000000000H1NoneSource operand is not SNaN;but #I is signaled (e.g.
forsqrt (-1.0))Single precision ordouble precision QNaNIndefiniteNoneNOTE:1. SNaN | 00400000H is a quiet NaN in single precision format (if SNaN is in single precision) andSNaN | 0008000000000000H is a quiet NaN in double precision format (if SNaN is in doubleprecision), obtained from the signaling NaN given as input.Vol. 1 E-11GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERSTable E-11. CVTPS2PD, CVTSS2SDSource OperandsMasked Result1QNaNQNaN1SNaNQNaN12Unmasked ResultQNaN11 (not an exception)NoneNOTES:1. The double precision output QNaN1 is created from the single precision input QNaN as follows:the sign bit is preserved, the 8-bit exponent FFH is replaced by the 11-bit exponent 7FFH, andthe 24-bit significand is extended to a 53-bit significand by appending 29 bits equal to 0.2. The double precision output QNaN1 is created from the single precision input SNaN as follows:the sign bit is preserved, the 8-bit exponent FFH is replaced by the 11-bit exponent 7FFH, andthe 24-bit significand is extended to a 53-bit significand by pending 29 bits equal to 0.
The second most significant bit of the significand is changed from 0 to 1 to convert the signaling NaNinto a quiet NaN.Table E-12. CVTPD2PS, CVTSD2SSSource OperandsMasked ResultUnmasked ResultQNaNQNaN11QNaN11 (not an exception)SNaNQNaN12NoneNOTES:1. The single precision output QNaN1 is created from the double precision input QNaN as follows:the sign bit is preserved, the 11-bit exponent 7FFH is replaced by the 8-bit exponent FFH, andthe 53-bit significand is truncated to a 24-bit significand by removing its 29 least significantbits.2. The single precision output QNaN1 is created from the double precision input SNaN as follows:the sign bit is preserved, the 11-bit exponent 7FFH is replaced by the 8-bit exponent FFH, andthe 53-bit significand is truncated to a 24-bit significand by removing its 29 least significantbits.
The second most significant bit of the significand is changed from 0 to 1 to convert the signaling NaN into a quiet NaN.E.4.2.3Condition Codes, Exception Flags, and Response for Masked andUnmasked Numeric ExceptionsIn the following, the masked response is what the processor provides when a maskedexception is raised by an SSE/SSE2/SSE3 numeric instruction. The same response isprovided by the floating-point emulator for SSE/SSE2/SSE3 numeric instructions,when certain components of the quadruple input operands generate exceptions thatare masked (the emulator also generates the correct answer, as specified by IEEEStandard 754 wherever applicable, in the case when no floating-point exceptionoccurs). The unmasked response is what the emulator provides to the user handlerfor those components of the packed operands of SSE/SSE2/SSE3 instructions thatraise unmasked exceptions.
Note that for pre-computation exceptions (floating-pointE-12 Vol. 1GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERSfaults), no result is provided to the user handler. For post-computation exceptions(floating-point traps), a result is provided to the user handler, as specified below.In the following tables, the result is denoted by 'res', with the understanding that forthe actual instruction, the destination coincides with the first source operand (exceptfor COMISS, UCOMISS, COMISD, and UCOMISD, whose destination is the EFLAGSregister).Table E-13. #I - Invalid OperationsInstructionConditionMasked ResponseADDPSADDPDADDSSADDSDHADDPSHADDPDsrc1 or src2 = SNaN1Refer to Table E-1 forNaN operands, #IA = 1ADDSUBPS (the src1 = +Inf, src2 = -Inf oradditionsrc1 = -Inf, src2 = +Infcomponent)ADDSUBPD (theadditioncomponent)res1 = QNaN Indefinite,#IA = 1SUBPSSUBPDSUBSSSUBSDHSUBPSHSUBPDRefer to Table E-1 for NaNoperands, #IA = 1src1 or src2 = SNaNADDSUBPS (the src1 = +Inf, src2 = +Inf orsubtractionsrc1 = -Inf, src2 = -Infcomponent)ADDSUBPD (thesubtractioncomponent)res = QNaN Indefinite,#IA = 1MULPSMULPDsrc1 or src2 = SNaNRefer to Table E-1 forNaN operands, #IA = 1MULSSMULSDsrc1 = ±Inf, src2 = ±0 orsrc1 = ±0, src2 = ±Infres = QNaN Indefinite,#IA = 1DIVPSDIVPDsrc1 or src2 = SNaNRefer to Table E-1 forNaN operands, #IA = 1DIVSSDIVSDsrc1 = ±Inf, src2 = ±Inf orsrc1 = ±0, src2 = ±0res = QNaN Indefinite,#IA = 1UnmaskedResponse andException Codesrc1, src2unchanged; #IA =1src1, src2unchanged; #IA =1src1, src2unchanged;#IA = 1src1, src2unchanged;#IA = 1Vol.
1 E-13GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERSTable E-13. #I - Invalid Operations (Contd.)InstructionConditionMasked ResponseUnmaskedResponse andException CodeSQRTPSSQRTPDSQRTSSSQRTSDsrc = SNaNRefer to Table E-10 forNaN operands, #IA = 1src unchanged,#IA = 1src < 0(note that -0 < 0 is false)res = QNaN Indefinite,#IA = 1MAXPSMAXSSMAXPDMAXSDsrc1 = NaN or src2 = NaNres = src2, #IA = 1src1, src2unchanged; #IA =1MINPSMINSSMINPDMINSDsrc1 = NaN or src2 = NaNres = src2, #IA = 1src1, src2unchanged; #IA =1E-14 Vol.
1GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERSTable E-13. #I - Invalid Operations (Contd.)InstructionConditionMasked ResponseUnmaskedResponse andException CodeCMPPS.LTCMPPS.LECMPPS.NLTCMPPS.NLECMPSS.LTCMPSS.LECMPSS.NLTCMPSS.NLECMPPD.LTCMPPD.LECMPPD.NLTCMPPD.NLECMPSD.LTCMPSD.LECMPSD.NLTCMPSD.NLEsrc1 = NaN or src2 = NaNRefer to Table E-4 andTable E-5 for NaNoperands; #IA = 1src1, src2unchanged; #IA =1COMISSCOMISDsrc1 = NaN or src2 = NaNRefer to Table E-6 for NaNoperandssrc1, src2, EFLAGSunchanged; #IA =1UCOMISSUCOMISDsrc1 = SNaN or src2 = SNaNRefer to Table E-7 for NaNoperandssrc1, src2, EFLAGSunchanged; #IA =1CVTPS2PICVTSS2SICVTPD2PICVTSD2SICVTPS2DQCVTPD2DQsrc = NaN, ±Inf, or|(src)rnd | > 7FFFFFFFH and(src)rnd ≠ 80000000Hres = Integer Indefinite,#IA = 1src unchanged,#IA = 1CVTTPS2PICVTTSS2SICVTTPD2PICVTTSD2SICVTTPS2DQCVTTPD2DQsrc = NaN, ±Inf, or|(src)rz | > 7FFFFFFFH and(src)rz ≠ 80000000Hres = Integer Indefinite,#IA = 1src unchanged,#IA = 1CVTPS2PDCVTSS2SDsrc = NANRefer to Table E-11 forNaN operandssrc unchanged,#IA = 1CVTPD2PSCVTSD2SSsrc = NANRefer to Table E-12 forNaN operandssrc unchanged,#IA = 1See Note2 for informationon rnd.See Note2 for informationon rz.Vol.
1 E-15GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERSTable E-13. #I - Invalid Operations (Contd.)InstructionConditionMasked ResponseUnmaskedResponse andException CodeNOTES:1. For Tables E-13 to E-18:- src denotes the single source operand of a unary operation.- src1, src2 denote the first and second source operand of a binary operation.- res denotes the numerical result of an operation.2. rnd signifies the user rounding mode from MXCSR, and rz signifies the rounding mode towardzero.
(truncate), when rounding a floating-point value to an integer. For more information, referto Table 4-8.3. For NAN encodings, see Table 4-3.Table E-14. #Z - Divide-by-ZeroInstructionConditionMasked ResponseDIVPSDIVSSDIVPDDIVPSsrc1 = finite non-zero (normal,or denormal)src2 = ±0res = ±Inf,#ZE = 1E-16 Vol. 1UnmaskedResponse andException Codesrc1, src2unchanged;#ZE = 1GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERSTable E-15.
#D - Denormal OperandInstructionConditionMasked ResponseADDPSADDPDADDSUBPSADDSUBPDHADDPSHADDPDSUBPSSUBPDHSUBPSHSUBPDMULPSMULPDDIVPSDIVPDSQRTPSSQRTPDMAXPSMAXPDMINPSMINPDCMPPSCMPPDADDSSADDSDSUBSSSUBSDMULSSMULSDDIVSSDIVSDSQRTSSSQRTSDMAXSSMAXSDMINSSMINSDCMPSSCMPSDCOMISSCOMISDUCOMISSUCOMISDCVTPS2PDsrc1 = denormal1 orsrc2 = denormal (andthe DAZ bit in MXCSRis 0)res = Result rounded tothe destination precisionand using the boundedexponent, but only if nounmasked postcomputation exceptionoccurs.Unmasked Responseand Exception Codesrc1, src2 unchanged;#DE = 1Note that SQRT,CVTPS2PD, CVTSS2SD,CVTPD2PS, CVTSD2SShave only 1 src.Vol.
1 E-17GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERSTable E-15. #D - Denormal Operand (Contd.)InstructionConditionMasked ResponseUnmasked Responseand Exception CodeCVTSS2SDCVTPD2PSCVTSD2SSNOTE:1. For denormal encodings, see Section 4.8.3.2, “Normalized and Denormalized Finite Numbers.”Table E-16. #O - Numeric OverflowInstructionConditionMasked ResponseADDPSADDSUBPSHADDPSSUBPSHSUBPSMULPSDIVPSADDSSSUBSSMULSSDIVSSCVTPD2PSCVTSD2SSRounded result> largest singleprecision finitenormal valueRoundingE-18 Vol.
1TonearestToward–∞Toward+∞Toward0SignResult & StatusFlags+-#OE = 1, #PE = 1res = + ∞res = – ∞+-#OE = 1, #PE = 1res = 1.11…1 * 2127res = – ∞+-#OE = 1, #PE = 1res = + ∞res = -1.11…1 * 2127+-#OE = 1, #PE = 1res = 1.11…1 * 2127res = -1.11…1 * 2127Unmasked Responseand Exception Coderes = (result calculatedwith unboundedexponent and rounded tothe destination precision)/ 2192#OE = 1#PE = 1 if the result isinexactGUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERSTable E-16. #O - Numeric Overflow (Contd.)InstructionConditionMasked ResponseADDPDADDSUBPDHADDPDSUBPDHSUBPDMULPDDIVPDADDSDSUBSDMULSDDIVSDRounded result> largest doubleprecision finitenormal valueRoundingTonearestToward–∞Toward+∞Toward0Sign+-Result & StatusFlags#OE = 1, #PE = 1res = + ∞res = – ∞+-#OE = 1, #PE = 1res = 1.11…1 *21023res = – ∞+-#OE = 1, #PE = 1res = + ∞res = -1.11…1 *21023+-Unmasked Responseand Exception Coderes = (result calculatedwith unboundedexponent and rounded tothe destination precision)/ 21536• #OE = 1• #PE = 1 if the result isinexact#OE = 1, #PE = 1res = 1.11…1 *21023res = -1.11…1 *21023Vol.
1 E-19GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERSTable E-17. #U - Numeric UnderflowInstructionConditionMasked ResponseADDPSADDSUBPSHADDPSSUBPSHSUBPSMULPSDIVPSADDSSSUBSSMULSSDIVSSCVTPD2PSCVTSD2SSResult calculated withunbounded exponent androunded to thedestination precision <smallest single precisionfinite normal value.res = ±0, denormal, ornormalADDPDADDSUBPDHADDPDSUBPDHSUBPDMULPDDIVPDADDSDSUBSDMULSDDIVSDResult calculated withunbounded exponent androunded to thedestination precision <smallest double precisionfinite normal value.res = ±0, denormal ornormalE-20 Vol.
1#UE = 1 and #PE = 1,but only if the result isinexact#UE = 1 and #PE = 1,but only if the result isinexactUnmasked Responseand Exception Coderes = (result calculatedwith unboundedexponent and rounded tothe destination precision)* 2192• #UE = 1• #PE = 1 if the result isinexactres = (result calculatedwith unboundedexponent and rounded tothe destination precision)* 21536• #UE = 1• #PE = 1 if the result isinexactGUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERSTable E-18.
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