Volume 1 Basic Architecture (794100), страница 71
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Looks for, reports on, and handles pre-computation exception conditions (invalidoperand, divide-by-zero, and denormal operand)2. Looks for, reports on, and handles post-computation exception conditions(numeric overflow, numeric underflow, and inexact result)If both pre- and post-computational exceptions are unmasked, it is possible for theprocessor to generate a SIMD floating-point exception (#XM) twice during the execution of an SSE, SSE2 or SSE3 instruction: once when it detects and handles a precomputational exception and when it detects a post-computational exception.11.5.3.1Handling Masked ExceptionsIf all exceptions are masked, the processor handles the exceptions it detects byplacing the masked result (or results for packed operands) in a destination operandVol.
1 11-23PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)and continuing program execution. The masked result may be a rounded normalizedvalue, signed infinity, a denormal finite number, zero, a QNaN floating-point indefinite, or a QNaN depending on the exception condition detected. In most cases, thecorresponding exception flag bit in MXCSR is also set. The one situation where anexception flag is not set is when an underflow condition is detected and it is notaccompanied by an inexact result.When operating on packed floating-point operands, the processor returns a maskedresult for each of the sub-operand computations and sets a separate set of internalexception flags for each computation. It then performs a logical-OR on the internalexception flag settings and sets the exception flags in the MXCSR register accordingto the results of OR operations.For example, Figure 11-9 shows the results of an MULPS instruction.
In the example,all SIMD floating-point exceptions are masked. Assume that a denormal exceptioncondition is detected prior to the multiplication of sub-operands X0 and Y0, no exception condition is detected for the multiplication of X1 and Y1, a numeric overflowexception condition is detected for the multiplication of X2 and Y2, and anotherdenormal exception is detected prior to the multiplication of sub-operands X3 andY3. Because denormal exceptions are masked, the processor uses the denormalsource values in the multiplications of (X0 and Y0) and of (X3 and Y3) passing theresults of the multiplications through to the destination operand. With the denormaloperand, the result of the X0 and Y0 computation is a normalized finite value, with noexceptions detected.
However, the X3 and Y3 computation produces a tiny andinexact result. This causes the corresponding internal numeric underflow andinexact-result exception flags to be set.X3Y3 (Denormal)MULPSTiny, Inexact, FiniteX2Y2MULPS∞X1X0 (Denormal)Y1MULPSY0MULPSNormalized Finite Normalized FiniteFigure 11-9. Example Masked Response for Packed OperationsFor the multiplication of X2 and Y2, the processor stores the floating-point ∞ in thedestination operand, and sets the corresponding internal sub-operand numeric overflow flag. The result of the X1 and Y1 multiplication is passed through to the destination operand, with no internal sub-operand exception flags being set. Following the11-24 Vol.
1PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)computations, the individual sub-operand exceptions flags for denormal operand,numeric underflow, inexact result, and numeric overflow are OR’d and the corresponding flags are set in the MXCSR register.The net result of this computation is that:•••••Multiplication of X0 and Y0 produces a normalized finite resultMultiplication of X1 and Y1 produces a normalized finite resultMultiplication of X2 and Y2 produces a floating-point ∞ resultMultiplication of X3 and Y3 produces a tiny, inexact, finite resultDenormal operand, numeric underflow, numeric underflow, and inexact resultflags are set in the MXCSR register11.5.3.2Handling Unmasked ExceptionsIf all exceptions are unmasked, the processor:1.
First detects any pre-computation exceptions: it ORs those exceptions, sets theappropriate exception flags, leaves the source and destination operandsunaltered, and goes to step 2. If it does not detect any pre-computationexceptions, it goes to step 5.2. Checks CR4.OSXMMEXCPT[bit 10].
If this flag is set, the processor goes to step3; if the flag is clear, it generates an invalid-opcode exception (#UD) and makesan implicit call to the invalid-opcode exception handler.3. Generates a SIMD floating-point exception (#XM) and makes an implicit call tothe SIMD floating-point exception handler.4. If the exception handler is able to fix the source operands that generated the precomputation exceptions or mask the condition in such a way as to allow theprocessor to continue executing the instruction, the processor resumesinstruction execution as described in step 5.5. Upon returning from the exception handler (or if no pre-computation exceptionswere detected), the processor checks for post-computation exceptions.
If theprocessor detects any post-computation exceptions: it ORs those exceptions,sets the appropriate exception flags, leaves the source and destination operandsunaltered, and repeats steps 2, 3, and 4.6. Upon returning from the exceptions handler in step 4 (or if no post-computationexceptions were detected), the processor completes the execution of theinstruction.The implication of this procedure is that for unmasked exceptions, the processor cangenerate a SIMD floating-point exception (#XM) twice: once if it detects pre-computation exception conditions and a second time if it detects post-computation exception conditions. For example, if SIMD floating-point exceptions are unmasked for thecomputation shown in Figure 11-9, the processor would generate one SIMD floatingpoint exception for denormal operand conditions and a second SIMD floating-pointVol.
1 11-25PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)exception for overflow and underflow (no inexact result exception would be generated because the multiplications of X0 and Y0 and of X1 and Y1 are exact).11.5.3.3Handling Combinations of Masked and Unmasked ExceptionsIn situations where both masked and unmasked exceptions are detected, theprocessor will set exception flags for the masked and the unmasked exceptions.However, it will not return masked results until after the processor has detected andhandled unmasked post-computation exceptions and returned from the exceptionhandler (as in step 6 above) to finish executing the instruction.11.5.4Handling SIMD Floating-Point Exceptions in SoftwareSection 4.9.3, “Typical Actions of a Floating-Point Exception Handler,” shows actionsthat may be carried out by a SIMD floating-point exception handler.
TheSSE/SSE2/SSE3 state is saved with the FXSAVE instruction (see Section 11.6.5,“Saving and Restoring the SSE/SSE2 State”).11.5.5Interaction of SIMD and x87 FPU Floating-Point ExceptionsSIMD floating-point exceptions are generated independently from x87 FPU floatingpoint exceptions. SIMD floating-point exceptions do not cause assertion of theFERR# pin (independent of the value of CR0.NE[bit 5]).
They ignore the assertionand deassertion of the IGNNE# pin.If applications use SSE/SSE2/SSE3 instructions along with x87 FPU instructions (inthe same task or program), consider the following:•SIMD floating-point exceptions are reported independently from the x87 FPUfloating-point exceptions. SIMD and x87 FPU floating-point exceptions can beunmasked independently.
Separate x87 FPU and SIMD floating-point exceptionhandlers must be provided if the same exception is unmasked for x87 FPU and forSSE/SSE2/SSE3 operations.•The rounding mode specified in the MXCSR register does not affect x87 FPUinstructions. Likewise, the rounding mode specified in the x87 FPU control worddoes not affect the SSE/SSE2/SSE3 instructions. To use the same roundingmode, the rounding control bits in the MXCSR register and in the x87 FPU controlword must be set explicitly to the same value.•The flush-to-zero mode set in the MXCSR register for SSE/SSE2/SSE3 instructions has no counterpart in the x87 FPU.
For compatibility with the x87 FPU, setthe flush-to-zero bit to 0.•The denormals-are-zeros mode set in the MXCSR register for SSE/SSE2/SSE3instructions has no counterpart in the x87 FPU. For compatibility with the x87FPU, set the denormals-are-zeros bit to 0.11-26 Vol. 1PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)•An application that expects to detect x87 FPU exceptions that occur during theexecution of x87 FPU instructions will not be notified if exceptions occurs duringthe execution of corresponding SSE/SSE2/SSE31 instructions, unless theexception masks that are enabled in the x87 FPU control word have also beenenabled in the MXCSR register and the application is capable of handling SIMDfloating-point exceptions (#XM).— Masked exceptions that occur during an SSE/SSE2/SSE3 library call cannotbe detected by unmasking the exceptions after the call (in an attempt togenerate the fault based on the fact that an exception flag is set).
A SIMDfloating-point exception flag that is set when the corresponding exception isunmasked will not generate a fault; only the next occurrence of thatunmasked exception will generate a fault.— An application which checks the x87 FPU status word to determine if anymasked exception flags were set during an x87 FPU library call will also needto check the MXCSR register to detect a similar occurrence of a maskedexception flag being set during an SSE/SSE2/SSE3 library call.11.6WRITING APPLICATIONS WITH SSE/SSE2EXTENSIONSThe following sections give some guidelines for writing application programs andoperating-system code that uses the SSE and SSE2 extensions.
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