Volume 1 Basic Architecture (794100), страница 74
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XMM registers can contain packed or scalar double-precision floatingpoint, packed single-precision floating-point, and 128-bit packed integer data types.The called procedure has no way of knowing the data types in XMM registersfollowing a call; so it is unlikely to use the correctly typed move instruction to storethe contents of XMM registers in memory or to restore the contents of XMM registersfrom memory.As described in Section 11.6.9, “Mixing Packed and Scalar Floating-Point and 128-BitSIMD Integer Instructions and Data,” executing a move instruction that does notmatch the type for the data being moved to/from XMM registers will be carried outcorrectly, but can lead to a greater instruction latency.11.6.11 Updating Existing MMX Technology RoutinesUsing 128-Bit SIMD Integer InstructionsSSE2 extensions extend all 64-bit MMX SIMD integer instructions to operate on 128bit SIMD integers using XMM registers.
The extended 128-bit SIMD integer instructions operate like the 64-bit SIMD integer instructions; this simplifies the porting ofMMX technology applications. However, there are considerations:•To take advantage of wider 128-bit SIMD integer instructions, MMX technologycode must be recompiled to reference the XMM registers instead of MMXregisters.•Computation instructions that reference memory operands that are not alignedon 16-byte boundaries should be replaced with an unaligned 128-bit load(MOVUDQ instruction) followed by a version of the same computation operationthat uses register instead of memory operands.
Use of 128-bit packed integercomputation instructions with memory operands that are not 16-byte alignedresults in a general protection exception (#GP).•Extension of the PSHUFW instruction (shuffle word across 64-bit integeroperand) across a full 128-bit operand is emulated by a combination of thefollowing instructions: PSHUFHW, PSHUFLW, and PSHUFD.•Use of the 64-bit shift by bit instructions (PSRLQ, PSLLQ) can be extended to 128bits in either of two ways:— Use of PSRLQ and PSLLQ, along with masking logic operations.— Rewriting the code sequence to use PSRLDQ and PSLLDQ (shift doublequadword operand by bytes)Vol.
1 11-35PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)•Loop counters need to be updated, since each 128-bit SIMD integer instructionoperates on twice the amount of data as its 64-bit SIMD integer counterpart.11.6.12 Branching on Arithmetic OperationsThere are no condition codes in SSE or SSE2 states. A packed-data comparisoninstruction generates a mask which can then be transferred to an integer register.The following code sequence provides an example of how to perform a conditionalbranch, based on the result of an SSE2 arithmetic operation.cmppdmovmskpdtestjneXMM0, XMM1EAX, XMM0EAX, 0,2BRANCH TARGET; generates a mask in XMM0; moves a 2 bit mask to eax; compare with desired resultThe COMISD and UCOMISD instructions update the EFLAGS as the result of a scalarcomparison.
A conditional branch can then be scheduled immediately followingCOMISD/UCOMISD.11.6.13 Cacheability Hint InstructionsSSE and SSE2 cacheability control instructions enable the programmer to controlprefetching, caching, loading and storing of data. When correctly used, these instructions improve application performance.To make efficient use of the processor’s super-scalar microarchitecture, a programneeds to provide a steady stream of data to the executing program to avoid stallingthe processor. PREFETCHh instructions minimize the latency of data accesses inperformance-critical sections of application code by allowing data to be fetched intothe processor cache hierarchy in advance of actual usage.PREFETCHh instructions do not change the user-visible semantics of a program,although they may affect performance.
The operation of these instructions is implementation-dependent. Programmers may need to tune code for each IA-32processor implementation. Excessive usage of PREFETCHh instructions may wastememory bandwidth and reduce performance. For more detailed information on theuse of prefetch hints, refer to Chapter 6, “Optimizing Cache Usage”, in the Intel® 64and IA-32 Architectures Optimization Reference Manual.The non-temporal store instructions (MOVNTI, MOVNTPD, MOVNTPS, MOVNTDQ,MOVNTQ, MASKMOVQ, and MASKMOVDQU) minimize cache pollution when writingnon-temporal data to memory (see Section 10.4.6.2, “Caching of Temporal vs.
NonTemporal Data,” and Section 10.4.6.1, “Cacheability Control Instructions”). Theyprevent non-temporal data from being written into processor caches on a store operation. These instructions are implementation specific. Programmers may have totune their applications for each IA-32 processor implementation to take advantage ofthese instructions.11-36 Vol. 1PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)Besides reducing cache pollution, the use of weakly-ordered memory types can beimportant under certain data sharing relationships, such as a producer-consumerrelationship. The use of weakly ordered memory can make the assembling of datamore efficient; but care must be taken to ensure that the consumer obtains the datathat the producer intended.
Some common usage models that may be affected in thisway by weakly-ordered stores are:•••Library functions that use weakly ordered memory to write resultsCompiler-generated code that writes weakly-ordered resultsHand-crafted codeThe degree to which a consumer of data knows that the data is weakly ordered canvary for these cases. As a result, the SFENCE or MFENCE instruction should be usedto ensure ordering between routines that produce weakly-ordered data and routinesthat consume the data. SFENCE and MFENCE provide a performance-efficient way toensure ordering by guaranteeing that every store instruction that precedesSFENCE/MFENCE in program order is globally visible before a store instruction thatfollows the fence.11.6.14 Effect of Instruction Prefixes on the SSE/SSE2 InstructionsTable 11-3 describes the effects of instruction prefixes on SSE and SSE2 instructions.(Table 11-3 also applies to SIMD integer and SIMD floating-point instructions inSSE3.) Unpredictable behavior can range from prefixes being treated as a reservedoperation on one generation of IA-32 processors to generating an invalid opcodeexception on another generation of processors.See also “Instruction Prefixes” in Chapter 2 of the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 2A, for complete description of instructionprefixes.NOTESome SSE/SSE2/SSE3 instructions have two-byte opcodes that areeither 2 bytes or 3 bytes in length.
Two-byte opcodes that are 3 bytesin length consist of: a mandatory prefix (F2H, F3H, or 66H), 0FH, andan opcode byte. See Table 11-3.Table 11-3. Effect of Prefixes on SSE, SSE2, and SSE3 InstructionsPrefix TypeAddress Size Prefix (67H)Effect on SSE, SSE2 and SSE3 InstructionsAffects instructions with a memory operand.Reserved for instructions without a memory operand andmay result in unpredictable behavior.Operand Size (66H)Reserved and may result in unpredictable behavior.Vol. 1 11-37PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)Table 11-3. Effect of Prefixes on SSE, SSE2, and SSE3 InstructionsPrefix TypeEffect on SSE, SSE2 and SSE3 InstructionsSegment Override(2EH,36H,3EH,26H,64H,65H)Affects instructions with a memory operand.Repeat Prefixes (F2H and F3H)Reserved and may result in unpredictable behavior.Lock Prefix (F0H)Reserved; generates invalid opcode exception (#UD).Branch Hint Prefixes(E2H andE3H)Reserved and may result in unpredictable behavior.11-38 Vol.
1Reserved for instructions without a memory operand andmay result in unpredictable behavior.CHAPTER 12PROGRAMMING WITHSSE3 AND SUPPLEMENTAL SSE3The Pentium 4 processor supporting Hyper-Threading Technology introducesStreaming SIMD Extensions 3 (SSE3). The Intel Xeon processor 5100 series, IntelCore 2 processor families introduced Supplemental Streaming SIMD Extensions 3(SSSE3).
This chapter describes SSE3/SSSE3 and provides information to assist inwriting application programs that use these extensions.12.1SSE3/SSSE3 PROGRAMMING ENVIRONMENT ANDDATA TYPESThe programming environment for using SSE3/SSSE3 is unchanged from that shownin Figure 3-1 and Figure 11-1.
SSE3/SSSE3 do not introduce new data types. XMMregisters are used to operate on packed integer data, single-precision floating-pointdata, or double-precision floating-point data.One SSE3 instruction uses the x87 FPU for x87-style programming. There are twoSSE3 instructions that use the general registers for thread synchronization. TheMXCSR register governs SIMD floating-point operations. Note, however, that thex87FPU control word does not affect the SSE3 instruction that is executed by the x87FPU (FISTTP), other than by unmasking an invalid operand or inexact result exception.12.1.1SSE3/SSSE3 in 64-Bit Mode and Compatibility ModeIn compatibility mode, SSE3/SSSE3 function like they do in protected mode.
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