Volume 1 Basic Architecture (794100), страница 70
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If an unmasked SIMD floating-point exception is generated and theOSXMMEXCEPT flag is set, the processor invokes a software exception handler bygenerating a SIMD floating-point exception (#XM). If the OSXMMEXCEPT bit is clear,the processor generates an invalid-opcode exception (#UD) on the first SSE or SSE2instruction that detects a SIMD floating-point exception condition.
See Section11.6.2, “Checking for SSE/SSE2 Support.”11.5.2SIMD Floating-Point Exception ConditionsThe following sections describe the conditions that cause a SIMD floating-pointexception to be generated and the masked response of the processor when theseconditions are detected.See Section 4.9.2, “Floating-Point Exception Priority,” for a description of the rules forexception precedence when more than one floating-point exception condition isdetected for an instruction.Vol. 1 11-19PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)11.5.2.1Invalid Operation Exception (#I)The floating-point invalid-operation exception (#I) occurs in response to an invalidarithmetic operand.
The flag (IE) and mask (IM) bits for the invalid operation exception are bits 0 and 7, respectively, in the MXCSR register.If the invalid-operation exception is masked, the processor returns a QNaN, QNaNfloating-point indefinite, integer indefinite, one of the source operands to the destination operand, or it sets the EFLAGS, depending on the operation being performed.When a value is returned to the destination operand, it overwrites the destinationregister specified by the instruction. Table 11-1 lists the invalid-arithmetic operationsthat the processor detects for instructions and the masked responses to these operations.Table 11-1.
Masked Responses of SSE/SSE2/SSE3 Instructions to Invalid ArithmeticOperationsConditionMasked ResponseADDPS, ADDSS, ADDPD, ADDSD, SUBPS, SUBSS,SUBPD, SUBSD, MULPS, MULSS, MULPD,MULSD, DIVPS, DIVSS, DIVPD, DIVSD,ADDSUBPD, ADDSUBPD, HADDPD, HADDPS,HSUBPD or HSUBPS instruction with an SNaNoperandReturn the SNaN converted to a QNaN; Refer toTable 4-7 for more detailsSQRTPS, SQRTSS, SQRTPD, or SQRTSD withSNaN operandsReturn the SNaN converted to a QNaNSQRTPS, SQRTSS, SQRTPD, or SQRTSD withnegative operands (except zero)Return the QNaN floating-point IndefiniteMAXPS, MAXSS, MAXPD, MAXSD, MINPS,MINSS, MINPD, or MINSD instruction with QNaNor SNaN operandsReturn the source 2 operand valueCMPPS, CMPSS, CMPPD or CMPSD instructionwith QNaN or SNaN operandsReturn a mask of all 0s (except for thepredicates “not-equal,” “unordered,” “not-lessthan,” or “not-less-than-or-equal,” which returnsa mask of all 1s)CVTPD2PS, CVTSD2SS, CVTPS2PD, CVTSS2SDwith SNaN operandsReturn the SNaN converted to a QNaNCOMISS or COMISD with QNaN or SNaNoperand(s)Set EFLAGS values to “not comparable”Addition of opposite signed infinities orsubtraction of like-signed infinitiesReturn the QNaN floating-point IndefiniteMultiplication of infinity by zeroReturn the QNaN floating-point IndefiniteDivide of (0/0) or ( ∞ / ∞ )Return the QNaN floating-point Indefinite11-20 Vol.
1PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)Table 11-1. Masked Responses of SSE/SSE2/SSE3 Instructions to Invalid ArithmeticOperations (Contd.)ConditionConversion to integer when the value in thesource register is a NaN, ∞, or exceeds therepresentable range for CVTPS2PI, CVTTPS2PI,CVTSS2SI, CVTTSS2SI, CVTPD2PI, CVTSD2SI,CVTPD2DQ, CVTTPD2PI, CVTTSD2SI,CVTTPD2DQ, CVTPS2DQ, or CVTTPS2DQMasked ResponseReturn the integer IndefiniteIf the invalid operation exception is not masked, a software exception handler isinvoked and the operands remain unchanged. See Section 11.5.4, “Handling SIMDFloating-Point Exceptions in Software.”Normally, when one or more of the source operands are QNaNs (and neither is anSNaN or in an unsupported format), an invalid-operation exception is not generated.The following instructions are exceptions to this rule: the COMISS and COMISDinstructions; and the CMPPS, CMPSS, CMPPD, and CMPSD instructions (when thepredicate is less than, less-than or equal, not less-than, or not less-than or equal).With these instructions, a QNaN source operand will generate an invalid-operationexception.The invalid-operation exception is not affected by the flush-to-zero mode or by thedenormals-are-zeros mode.11.5.2.2Denormal-Operand Exception (#D)The processor signals the denormal-operand exception if an arithmetic instructionattempts to operate on a denormal operand.
The flag (DE) and mask (DM) bits forthe denormal-operand exception are bits 1 and 8, respectively, in the MXCSRregister.The CVTPI2PD, CVTPD2PI, CVTTPD2PI, CVTDQ2PD, CVTPD2DQ, CVTTPD2DQ,CVTSI2SD, CVTSD2SI, CVTTSD2SI, CVTPI2PS, CVTPS2PI, CVTTPS2PI, CVTSS2SI,CVTTSS2SI, CVTSI2SS, CVTDQ2PS, CVTPS2DQ, and CVTTPS2DQ conversion instructions do not signal denormal exceptions. The RCPSS, RCPPS, RSQRTSS, andRSQRTPS instructions do not signal any kind of floating-point exception.The denormals-are-zero flag (bit 6) of the MXCSR register provides an additionaloption for handling denormal-operand exceptions. When this flag is set, denormalsource operands are automatically converted to zeros with the sign of the sourceoperand (see Section 10.2.3.4, “Denormals-Are-Zeros”).
The denormal operandexception is not affected by the flush-to-zero mode.See Section 4.9.1.2, “Denormal Operand Exception (#D),” for more informationabout the denormal exception. See Section 11.5.4, “Handling SIMD Floating-PointExceptions in Software,” for information on handling unmasked exceptions.Vol. 1 11-21PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)11.5.2.3Divide-By-Zero Exception (#Z)The processor reports a divide-by-zero exception when a DIVPS, DIVSS, DIVPD orDIVSD instruction attempts to divide a finite non-zero operand by 0. The flag (ZE)and mask (ZM) bits for the divide-by-zero exception are bits 2 and 9, respectively, inthe MXCSR register.See Section 4.9.1.3, “Divide-By-Zero Exception (#Z),” for more information aboutthe divide-by-zero exception.
See Section 11.5.4, “Handling SIMD Floating-PointExceptions in Software,” for information on handling unmasked exceptions.The divide-by-zero exception is not affected by the flush-to-zero mode or by thedenormals-are-zeros mode.11.5.2.4Numeric Overflow Exception (#O)The processor reports a numeric overflow exception whenever the rounded result ofan arithmetic instruction exceeds the largest allowable finite value that fits in thedestination operand. This exception can be generated with the ADDPS, ADDSS,ADDPD, ADDSD, SUBPS, SUBSS, SUBPD, SUBSD, MULPS, MULSS, MULPD, MULSD,DIVPS, DIVSS, DIVPD, DIVSD, CVTPD2PS, CVTSD2SS, ADDSUBPD, ADDSUBPS,HADDPD, HADDPS, HSUBPD and HSUBPS instructions.
The flag (OE) and mask (OM)bits for the numeric overflow exception are bits 3 and 10, respectively, in the MXCSRregister.See Section 4.9.1.4, “Numeric Overflow Exception (#O),” for more information aboutthe numeric-overflow exception. See Section 11.5.4, “Handling SIMD Floating-PointExceptions in Software,” for information on handling unmasked exceptions.The numeric overflow exception is not affected by the flush-to-zero mode or by thedenormals-are-zeros mode.11.5.2.5Numeric Underflow Exception (#U)The processor reports a numeric underflow exception whenever the rounded result ofan arithmetic instruction is less than the smallest possible normalized, finite valuethat will fit in the destination operand and the numeric-underflow exception is notmasked.
If the numeric underflow exception is masked, both underflow and theinexact-result condition must be detected before numeric underflow is reported. Thisexception can be generated with the ADDPS, ADDSS, ADDPD, ADDSD, SUBPS,SUBSS, SUBPD, SUBSD, MULPS, MULSS, MULPD, MULSD, DIVPS, DIVSS, DIVPD,DIVSD, CVTPD2PS, CVTSD2SS, ADDSUBPD, ADDSUBPS, HADDPD, HADDPS,HSUBPD, and HSUBPS instructions. The flag (UE) and mask (UM) bits for the numericunderflow exception are bits 4 and 11, respectively, in the MXCSR register.The flush-to-zero flag (bit 15) of the MXCSR register provides an additional option forhandling numeric underflow exceptions. When this flag is set and the numeric underflow exception is masked, tiny results (results that trigger the underflow exception)are returned as a zero with the sign of the true result (see Section 10.2.3.3, “Flush-11-22 Vol.
1PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)To-Zero”). The numeric underflow exception is not affected by the denormals-arezero mode.See Section 4.9.1.5, “Numeric Underflow Exception (#U),” for more informationabout the numeric underflow exception. See Section 11.5.4, “Handling SIMDFloating-Point Exceptions in Software,” for information on handling unmaskedexceptions.11.5.2.6Inexact-Result (Precision) Exception (#P)The inexact-result exception (also called the precision exception) occurs if the resultof an operation is not exactly representable in the destination format. For example,the fraction 1/3 cannot be precisely represented in binary form. This exceptionoccurs frequently and indicates that some (normally acceptable) accuracy has beenlost.
The exception is supported for applications that need to perform exact arithmetic only. Because the rounded result is generally satisfactory for most applications, this exception is commonly masked.The flag (PE) and mask (PM) bits for the inexact-result exception are bits 2 and 12,respectively, in the MXCSR register.See Section 4.9.1.6, “Inexact-Result (Precision) Exception (#P),” for more information about the inexact-result exception.
See Section 11.5.4, “Handling SIMDFloating-Point Exceptions in Software,” for information on handling unmasked exceptions.In flush-to-zero mode, the inexact result exception is reported. The inexact resultexception is not affected by the denormals-are-zero mode.11.5.3Generating SIMD Floating-Point ExceptionsWhen the processor executes a packed or scalar floating-point instruction, it looks forand reports on SIMD floating-point exception conditions using two sequential steps:1.
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