USP_6887801 (1063233), страница 3
Текст из файла (страница 3)
Phys. vol. 33 (1994) pp. L227—L229, Part 2, No. 2B,and Systems, vol. 5, No. 4, Dec. 1994, pp. 65—95.Naone R.L., et al., “Tapered—apertures for high—ef?ciencyrniniature VCSELs”, LEOS neWsletter, vol. 13, No. 4, pp.1—5, Aug. 1999.Nugent et al., “Self—Pulsations in Vertical—Cavity Surface—Ernitting Lasers”, Electronic Letters, vol. 31, No. 1, Jan.5, 1995, pp. 43—44.Oh, T. H.
et al., “Single—Mode Operation in AntiguidedVertical—Cavity Surface—Ernitting Laser Using a LoW—TernFeb. 15, 1994.Tu, Li—Wei et al., “Transparent conductive rnetal—oXidecontacts in vertical—injection top—ernitting quantum welllasers”, Appl. Phys. Lett. 58(8) Feb. 25, 1991, pp. 790—792.Weider, H.H., “Fermi level and surface barrier of GaxlnlixAsalloys,” Applied Physics Letters, vol. 38, No. 3, pp.170—171, Feb.
1, 1981.WipiejeWski, et al., “VCSELs for datacorn applications,”Invited Paper, Part of the SPIE Conference on Vertical—Cavperature GroWn AlGaAs Dielectric Aperture”, IEEE Photon.ity Surface—Ernitting Lasers III, San Jose, California, SPIETechnol. Lett. 10(8), 1064—1066 (1998).Osinski, et al., “Temperature and Thickness Dependence ofvol. 3627, pp. 14—22, Jan. 1999.Y. M. Yang et al., “UltraloW Threshold Current VerticalCavity Surface Ernitting Lasers Obtained With SelectiveOxidation”, Elect. Lett. , vol.
31, No. 11, pp. 886—888, MaySteam OXidation of AIAs in Cylindrical Mesa Structure,”IEEE Photonics Technology Letters, vol. 13, No. 7, pp.687—689, Jul. 2001.25, 1995.US 6,887,801 B2Page 5Yablonovitch et al., “Photonic Bandgap Structures”, J. Opt.Soc. Am. B., vol. 10, No. 2, pp. 283—295, Feb. 1993.Young et al., “Enhanced Performance of Offset—Gain HighBarrier Vertical—Cavity Surface—Ernitting Lasers”, IEEE J.Quantum Electron, vol. 29, No. 6, pp. 2013—2022, Jun.1993.US.
Appl. No. 09/751,422, ?led Dec. 29, 2000, entitled“Spatially, Modulated Re?ector for an OptoelectronicDevice”.U.S. Appl. No. 2002/0154675 A1, entitled “Reliability—Enhancing Layers for Vertical Cavity Surface EmittingLasers”, Publication date Oct. 24, 2002.US. Appl. No. 2001/0004414 A1, entitled, “Coupling Con?guration,” Publication date Jun. 21, 2001.“Resonant Re?ector for use With Optoelectronic Devices”.U.S. Appl.
No. 09/751,423, ?led Dec. 29, 2000, entitled* cited by eXarninerU.S. PatentMay 3, 2005Sheet 1 0f 3US 6,887,801 B2Prior Art Process Results300250Thiucknmes,200150—°— 4 inch Wafer——a— 3 inch Wafer50O.511.522.5Distance, inFIG. 133.54U.S. PatentMay 3,2005Sheet 2 of3US 6,887,801 B2U.S. PatentMay 3,2005Sheet 3 of3US 6,887,801 B25058526% l‘?565a 65 54 [JC62FIG. 47058 56 52/\‘J2// /’ //////4l///666AFIG.
5OdwEocx:F.150.100Distance, inFIG. 6p50{US 6,887,801 B212EDGE BEAD CONTROL METHOD ANDAPPARATUSphotoresist layer. A ?rst illustrative embodiment includes aWafer holder designed to hold a Wafer While photoresistspinning or other Wafer processing steps are performed. TheWafer holder may have a pocket shaped and designed toFIELD OF THE INVENTIONreceive a Wafer of a particular siZe. In a further embodiment,the Wafer holder may be shaped such that it may be receivedby Wafer processing apparatuses and treated as if the comThe present invention is related to the ?eld of microfabrication. In particular, the present invention is related tomethods for using and handling Wafers.BACKGROUND10aids in containing the spread of photoresist and in releasinga Wafer from the holder.Another illustrative embodiment includes a method ofSeveral microfabrication processes call for the use of verythick layers of photoresist.
Typically, photoresist layers areapplied to Wafers by a spinning process. An amount ofphotoresist is applied in liquid form to a Wafer, and the Waferbination Wafer holder and Wafer of a ?rst siZe is a Wafer ofa different siZe from the ?rst siZe. In yet anotherembodiment, the Wafer may include an outer groove Which15is spun at a predetermined speed for some period of time tospread the photoresist across the Wafer surface. A commonpreparing a Wafer for a processing step. The method mayinclude providing a Wafer holder adapted to receive theWafer.
The method may further include placing the Wafer inthe holder, and then performing a process step such as, forproblem for thick layers is the formation of an edge bead,eXample, spinning photoresist onto the Wafer or other lithogWhich is a marked increase in thickness near the outer edgeraphy and/or epitaXy or material deposition steps, etchingof the Wafer. Signi?cant variation in the photoresist thicksteps, grinding, or the like.
The method may also includesecuring the Wafer in the holder by use of a mechanicalness creates problems in eXposure and development ofphotoresist during lithography as Well as variations in ?nished die characteristics across a given Wafer. In particular,When using a contact mask, a large edge bead can preventdirect contact across a signi?cant area of the Wafer, reducingdevice or by the application of a suction or vacuum force.Yet another illustrative embodiment includes a method for25resolution in lithography.FIG. 1 shoWs a graphical representation of the edgethickness for three inch and four inch Wafers on Which a veryreducing edge bead thickness during spinning of a photoresist layer.
The method may include providing a Waferholder adapted to receive a Wafer and bold the Wafer duringa photoresist spinning step. The method may also includecon?guring the Wafer holder to receive a Wafer of a ?rst siZeand siZing the Wafer holder to resemble a Wafer of a secondthick layer has been spun in a prior art process. The dashedlines indicate illustrative upper and loWer acceptable boundssiZe that is larger than the ?rst siZe.for the photoresist layers. The acceptable bounds may varyBRIEF DESCRIPTION OF THE DRAWINGSWidely from one process to another.
The useful area 10 forthe four inch Wafer has a diameter of about 2.375 inches,While the useful area 12 for the three inch Wafer has aFIG. 1 is a graph representing the pro?le of a thickdiameter of about 1.5 inches. Approximating the useful areas10, 20 as circular, the percentage of the four inch Wafer areathat is useful area 10 is about 35%, While the percentage ofthe three inch Wafer area that is useful area 20 is about 25%.A further problem is that a limiting factor on edge bead siZe35is the centrifugal force on the photoresist during spinning;for small Wafers, the centrifugal forces generated are40FIG.
2 is an elevation vieW of a Wafer holding apparatusin accordance With an illustrative embodiment of the presentinvention;45harm, and eXtra time in terms of machine usage and personnel hours.In several processes, including, for eXample, a number ofThe folloWing detailed description should be read With55large Wafers that many neW microfabrication processmachines are made to process. While many Si Wafer processes for integrated circuitry noW use or are con?gured toreference to the draWings. The draWings, Which are notnecessarily to scale, depict illustrative embodiments and arenot intended to limit the scope of the invention.FIG. 2 is an elevation vieW of a Wafer holding apparatusin accordance With an illustrative embodiment of the presentinvention.
The Wafer holder 30 includes a recessed area oruse eight inch or larger Wafers, specialty processes such aspocket 32. The pocket 32 includes a channel 34 Which issome research and development as Well as VSCEL fabrication processes make use of three, four or siX inch Wafers.?uidly connected to a number of vacuum holes 36. A raisedouter portion 38 de?nes the pocket 32. In use, a Wafer isplaced into the pocket 32 and a vacuum force may be appliedSUMMARYand effects of an edge bead on the pro?le of a thickphotoresist spun on the surface; andFIG. 6 is a graph representing the pro?le of a thickDETAILED DESCRIPTION OF SEVERALEMBODIMENTSprocesses, thinned Wafers are used. For eXample, rather thanusing a typical 500 micron thick Wafer, some processes useWafers that are about 300 microns thick. These thinnedThe present invention, in an illustrative embodiment,includes an apparatus Which aids in reducing the incidenceFIG.
4 is a cross sectional vieW of a Working embodiment;FIG. 5 is a cross sectional vieW of the Working embodiment from FIG. 4 With a Wafer inserted in the pocket andphotoresist layer applied using a Working embodiment of thepresent invention.vertical cavity surface emitting laser (VCSEL) fabricationWafers tend to be fragile. Further, some specialiZedprocesses, including VCSEL fabrication, make use of special Wafers that are relatively small in comparison to theFIG. 3 is a cross sectional vieW taken along line 3—3 ofFIG.
2;reduced by reduced radius of the Wafer edge versus a largerWafer. These loW percentages reduce chip yield from eachindividual Wafer, increasing production costs by any ofseveral measures, including Wasted goods, environmentalphotoresist layer applied using a prior art process to differentsiZe Wafers;65using the channel 34 and vacuum holes 36. The use of achannel 34 and vacuum holes 36 is merely illustrative of oneof many Ways a vacuum force may be used to secure a Waferinto the pocket 32.
The vacuum force/suction may includeUS 6,887,801 B234simply using a pressure Which is reduced relative to thesurrounding atmosphere and need not mean the applicationthe material Within desired tolerances. Some example compatibility considerations may include durability or strength,density/Weight, melting or plastic deformation temperatures,adherence to photoresist, electrically insulative properties,of some certain level of vacuum pressure. Additional channels may also be provided in various locations such as, forexample, that illustrated in the Working embodiment beloW.In other embodiments, other Wafer securing apparatusesor resistance to etching chemicals.
In the Working embodiment explained beloW, the illustrative holder Was constructed of aluminum.In several embodiments, the Wafer holder 30 is used Withor features may be used to replace the channel 34 andvacuum holes 36. For example, clips may be providedaround the outside of the pocket 32. AWafer may have a holeor holes drilled in, and a screW used to hold the Wafer intodevices that apply a suction through channels on a surface.10the pocket 32. Pressure may be provided from the peripheryof the pocket 32, for example, With a set screW extendingthrough the raised outer portion 38. A tab or tabs may beto Wafers placed on a rotatable surface.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
