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3Influence of Immersion Lithographyon Wafer Edge DefectivityK. Jami, I. Pollentier, S. Vedula and G. Blumenstock1KLA-Tencor2IMEC1USA2Belgium1. IntroductionIn semiconductor manufacturing, the control of defects at the edge of the wafer is a keyfactor to keep the number of yielding die as high as possible per wafer. Using drylithography, this control is typically done by an edge bead removal (EBR) process, which isunderstood well. The recent production introduction of immersion lithography howeverchanges this situation significantly. During immersion exposure, the wafer edge is locally incontact with water from the immersion hood, and particles can then be transported backand forth from the wafer edge area to the scanner wafer stage. Material in the EBR regioncan also potentially be damaged by the dynamic force of the immersion hood movement.
Inthis chapter, we have investigated the impact of immersion lithography on wafer edgedefectivity. In the past, such work has been limited to the inspection of the flat top part ofthe wafer edge, due to the inspection challenges at the curved wafer edge and lack of acomprehensive defect inspection solution.
The development of edge inspection & metrologytools now allows us to probe this area of the wafer.This study used KLA-Tencor's VisEdge CV300-R, an automated edge inspection system thatprovides full wafer edge inspection (top, side, and bottom) using laser-illumination andmulti-sensor detection, and where defects can be classified with Automated DefectClassification (ADC) software. In addition to defectivity capture, the tool performssimultaneous, multi-layer, film edge and EBR metrology, indicating the distance from thewafer edge or wafer top depending on the location of the film/EBR edge.
It also can reviewdefects using an integrated, hi-resolution microscope.In this paper the impact from immersion lithography towards wafer edge defectivity isinvestigated. The work revealed several key factors related to wafer edge related defectivitycontrol: choice of resist, optimization of EBR recipes, scanner and immersion-fluidcontamination, wafer handling and device processing procedures. Understanding themechanisms of wafer edge related immersion defects is believed to be critical to thesuccessful integration of the immersion process into semiconductor manufacturing.2. Process control at the wafer edgeIn semiconductor manufacturing, control of the process at the wafer edge is a key factor indetermining the total number of yielding die on a wafer.
The removal of photoresist fromSource: Lithography, Book edited by: Michael Wang,ISBN 978-953-307-064-3, pp. 656, February 2010, INTECH, Croatia, downloaded from SCIYO.COMwww.intechopen.com34Lithographythe wafer backside and edges is especially important to avoid contact between the resist andthe scanner stage or wafer handling hardware. Typically, a solvent EBR rinse is the last stepin the coating recipe: the combination of a solvent stream from a static nozzle toward thewafer back side and a dynamic nozzle toward the wafer front side dissolves the resist up toa few millimeters from the wafer’s outer edge.
The desired position of the EBR materialedge at top side (the so-called EBR-width) can depend on the coated material (e.g.,antireflective topcoat vs. photoresist material) and/or on the layer within the device: forexample, a contact hole lithography process might use a slightly different EBR width thanthe gate process. To increase die yield, it is desirable to have EBR widths that are as small aspossible.Immersion lithography [1-4] has changed the way we view defectivity issues at the wafer edgesignificantly. During the immersion exposure sequence, the wafer edge is in contact with thewater from the immersion hood (IH), introducing additional concerns beyond direct contact ofresist with the scanner.
First, when the IH is scanning in the EBR region, its movement candamage material edges (Fig. 1a). IMEC’s program on immersion lithography found that, forexample, photoresist material can partially peel off during the IH pass (Fig. 1b).Fig. 1. a) Schematic representation of possible defect issues with immersion lithography;b) example of damaged photoresist material inspected with top-down optical microscope;and c) example of damaged residues at the wafer edge, inspected by tilted SEM (45°).A second concern involves the cleanliness of the wafer edge outside the EBR edges.
The IHpass wets not only the near-edge top surface, but also the curved wafer edge and even partof the bottom surface. Defects can be released from this area and re-deposited either on thewafer or on the wafer stage. In the first case, there will be a direct impact on the waferdefectivity. In the latter case, defects present on the wafer stage can be transported ontowafers in subsequent wafer processing.
IMEC’s program on immersion lithography foundthat resist residues left on the curved wafer part by an incomplete EBR step can be damagedby the IH pass, releasing fragments into the system (Fig. 1c).Traditional defect inspection techniques have serious limitations when monitoring thesenew issues. Conventional dark field or bright field inspection tools cannot access the waferedge since these systems typically have an edge exclusion of ~3mm.
While microscopy toolscan inspect the edge area, they can only give qualitative information with limited sampling.www.intechopen.comInfluence of Immersion Lithography on Wafer Edge Defectivit353. Technology for wafer edge defect inspectionThe new measurement system for wafer edge defect inspection (Fig. 2) is based on a lasersource directed to the wafer edge surface. Three detectors simultaneously collect thescattered light, the specular or reflected light and the phase difference between differentpolarization states.
As the laser scans the wafer edge surface, each signal can be convertedinto an image. Each type of defect produces a specific combination of signals from the threedetection channels, allowing automated defect classification.Fig. 2. Schematic representation of the VisEdge measurement principle.3. Imaging of the wafer edgeImaging covers the entire edge region including the following areas: ~5mm bottom nearedge, bottom bevel, apex, top bevel, and ~5mm top near-edge.
Scanning generates acontinuous high-resolution image for the entire wafer edge, which can be represented as aMercator projection: an unfolding of the wafer edge surface into a flat plane. Excursions ineccentricity and/or in EBR width, which might result in a layer’s edge ending on the wrongunderlying substrate, can be easily monitored using this kind of inspection.For wafer edge cleanliness, a high-resolution view of the wafer edge is typically more useful.Here, the images view only a few millimeter of the edge.
Figure 3 uses this representation toshow resist flakes observed along the apex-bevel regions in the specular channel.4. Immersion defect process characterization and optimizationAs indicated in the introduction, immersion-related defects at the wafer edge can be due toedge damage to the coated material in the EBR area, from the IH passing over this region.On the other hand, defects can be caused by transport of particles present on the bevel.These might be released by forces of the immersion hood, transported by the water in thehood, and re-deposited on the wafer and/or stage.
This work focuses on the latter, and inparticular on the flake defects observed in past work [5].5. Edge region flake defectsFlake defects are related to material residues that are present on the wafer edge aftercoating. Typically, these residues are only present on the apex of the bevel, and therefore arewww.intechopen.com36LithographyFig.
3. Example of a specular image using the new technology showing part of the bevel/apex region. This kind of representation is valuable for the evaluation of wafer edge quality.difficult to detect by conventional top-down inspection methods. The residues result from anon-optimized EBR process: since the coated material on the wafer edge can be significantlythicker than on the flat top region, an insufficient solvent supply can leave edge residueswhile the top surface is clean. This phenomenon is more commonly observed withphotoresist materials, rather than with BARC and topcoat materials.The morphology of edge residues can depend on the resist. For some resists, the residue canbe quite uniform along the apex. For other resists, large areas of thick residues are combinedwith areas with thin residues.Once detected, the problem can be solved by adjusting the EBR recipe.
Because making theEBR recipe longer limits the throughput of the immersion cluster, however, fabs try to avoidthis adjustment if possible, there is a clear risk of processing wafers with resist residues overto the immersion scanner.When wafers with resist residues are exposed on an immersion scanner, it is difficult topredict if the IH pass over the edge of the wafer will damage the resist residue, and if (partof) the residues will redeposit on the wafer top-side or on the scanner wafer stage. TiltedSEM review suggested qualitatively that such damage can happen with certain resists.6. Experimental conditions of edge flake characterizationWe experimented with three resists with different chemistries (Fig.
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