Donald E. Thomas - The Verilog Hardware Description Language, Fifth Edition

The Verilog® Hardware Description Language,Fifth EditionThe Verilog® Hardware Description Language,Fifth EditionDonald E. ThomasECE DepartmentCarnegie Mellon UniversityPittsburgh, PAPhilip R. MoorbyCo-design Automation, Inc.www.co-design.comVerilog® is a registered trade mark of Cadence Design Systems, Inc.eBook ISBN:Print ISBN:0-306-47666-51-4020-7089-6©2002 Kluwer Academic PublishersNew York, Boston, Dordrecht, London, MoscowPrint ©2002 Kluwer Academic PublishersDordrechtAll rights reservedNo part of this eBook may be reproduced or transmitted in any form or by any means, electronic,mechanical, recording, or otherwise, without written consent from the PublisherCreated in the United States of AmericaVisit Kluwer Online at:and Kluwer's eBookstore at:http://kluweronline.comhttp://ebooks.kluweronline.comTo Sandie,and John and Holland,and Jill.PrefaceFrom the Old to the NewAcknowledgments1Verilog –A Tutorial IntroductionGetting StartedA Structural DescriptionSimulating the binaryToESeg DriverCreating Ports For the ModuleCreating a Testbench For a ModuleBehavioral Modeling of Combinational CircuitsProcedural ModelsRules for Synthesizing Combinational CircuitsProcedural Modeling of Clocked Sequential CircuitsModeling Finite State MachinesRules for Synthesizing Sequential SystemsNon-Blocking Assignment ("<=")Module HierarchyThe CounterA Clock for the SystemTying the Whole Circuit TogetherTying Behavioral and Structural Models TogetherSummaryExercises2xvxviixxiLogic SynthesisOverview of SynthesisRegister-Transfer Level SystemsDisclaimerCombinational Logic Using Gates andContinuous AssignProcedural Statements to Specify Combinational LogicThe Basics122478111213141518192121212225272835353536374040The Verilog Hardware Description LanguageviiiComplications — Inferred LatchesUsing Case StatementsSpecifying Don' t Care SituationsProcedural Loop ConstructsInferring Sequential ElementsLatch InferencesFlip Flop InferencesSummaryInferring Tri-State DevicesDescribing Finite State MachinesAn Example of a Finite State MachineAn Alternate Approach to FSM SpecificationFinite State Machine and DatapathA Simple ComputationA Datapath For Our SystemDetails of the Functional Datapath ModulesWiring the Datapath TogetherSpecifying the FSMSummary on Logic SynthesisExercises3Behavioral ModelingProcess ModelIf-Then-ElseWhere Does The ELSE Belong?The Conditional OperatorLoopsFour Basic Loop StatementsExiting Loops on Exceptional ConditionsMulti-way BranchingIf-Else-IfCaseComparison of Case and If-Else-IfCasez and CasexFunctions and TasksTasksFunctionsA Structural ViewRules of Scope and Hierarchical NamesRules of ScopeHierarchical Names424344464848505252535356585858606163666873737580818282858686868990919397100102102105ixSummaryExercises4Concurrent ProcessesConcurrent ProcessesEventsEvent Control StatementNamed EventsThe Wait StatementA Complete Producer-Consumer HandshakeComparison of the Wait and While StatementsComparison of Wait and Event Control StatementsA Concurrent Process ExampleA Simple Pipelined ProcessorThe Basic ProcessorSynchronization Between PipestagesDisabling Named BlocksIntra-Assignment Control and Timing EventsProcedural Continuous AssignmentSequential and Parallel BlocksExercises5Module HierarchyModule Instantiation and Port SpecificationsParametersArrays of InstancesGenerate BlocksExercises106106109109111112113116117120121122128128130132134136138140143143146150151154The Verilog Hardware Description Languagex6Logic Level ModelingIntroductionLogic Gates and NetsModeling Using Primitive Logic GatesFour-Level Logic ValuesNetsA Logic Level ExampleContinuous AssignmentBehavioral Modeling of Combinational CircuitsNet and Continuous Assign DeclarationsA Mixed Behavioral/Structural ExampleLogic Delay ModelingA Gate Level Modeling ExampleGate and Net DelaysSpecifying Time UnitsMinimum, Typical, and Maximum DelaysDelay Paths Across a ModuleSummary of Assignment StatementsSummaryExercises7Cycle-Accurate SpecificationCycle-Accurate Behavioral DescriptionsSpecification ApproachA Few NotesCycle-Accurate SpecificationInputs and Outputs of an Always BlockInput/Output Relationships of an Always BlockSpecifying the Reset FunctionMealy/Moore Machine SpecificationsA Complex Control SpecificationData and Control Path Trade-offsIntroduction to Behavioral SynthesisSummary157157158159162163166171172174176180181182185186187189190191195195195197198198199202203204204209210xi8Advanced TimingVerilog Timing ModelsBasic Model of a SimulatorGate Level SimulationTowards a More General ModelScheduling Behavioral ModelsNon-Deterministic Behavior of theSimulation AlgorithmNear a Black HoleIt's a Concurrent LanguageNon-Blocking Procedural AssignmentsContrasting Blocking and Non-Blocking AssignmentsPrevalent Usage of the Non-Blocking AssignmentExtending the Event-Driven Scheduling AlgorithmIllustrating Non-Blocking AssignmentsSummaryExercises9User-Defined PrimitivesCombinational PrimitivesBasic Features of User-Defined PrimitivesDescribing Combinational Logic CircuitsSequential PrimitivesLevel-Sensitive PrimitivesEdge-Sensitive PrimitivesShorthand NotationMixed Level- and Edge-Sensitive PrimitivesSummaryExercises211211214215215218220221223226226227228231233234239240240242243244244246246249249The Verilog Hardware Description Languagexii10Switch Level ModelingA Dynamic MOS Shift Register ExampleSwitch Level ModelingStrength ModelingStrength DefinitionsAn Example Using StrengthsResistive MOS GatesAmbiguous StrengthsIllustrations of Ambiguous StrengthsThe Underlying CalculationsThe miniSim ExampleOverviewThe miniSim SourceSimulation ResultsSummaryExercises11ProjectsModeling Power DissipationModeling Power DissipationWhat to doStepsA Floppy Disk ControllerIntroductionDisk FormatFunction DescriptionsReality Sets In…Everything You Always Wanted to Know about CRC'sSupporting Verilog ModulesAppendix A: Tutorial Questions and DiscussionStructural DescriptionsTestbench ModulesCombinational Circuits Using always251251256256259260262263264265270270271280281281283283284284285286286287288291291292293293303303xiiiSequential CircuitsHierarchical Descriptions305308Appendix B: Lexical Conventions309White Space and CommentsOperatorsNumbersStringsIdentifiers, System Names, and KeywordsAppendix C: Verilog OperatorsTable of OperatorsOperator PrecedenceOperator Truth TablesExpression Bit LengthsAppendix D: Verilog Gate TypesLogic GatesBUF and NOT GatesBUFIF and NOTIF GatesMOS GatesBidirectional GatesCMOS GatesPullup and Pulldown GatesAppendix E: Registers, Memories, Integers,and TimeRegistersMemoriesIntegers and TimesAppendix F: System Tasks and FunctionsDisplay and Write TasksContinuous MonitoringStrobed MonitoringFile OutputSimulation TimeStop and FinishRandomReading Data From Disk FilesAppendix G: Formal Syntax DefinitionTutorial Guide to Formal Syntax Specification309310310311312315315320321322323323325326327328328328329329330331333333334335335336336336337339339xivThe Verilog Hardware Description LanguageSource textDeclarationsPrimitive instancesModule and generated instantiationUDP declaration and instantiationBehavioral statementsSpecify sectionExpressionsGeneralIndex343346351353355355359365370373PrefaceThe Verilog language is a hardware description language that provides a means ofspecifying a digital system at a wide range of levels of abstraction.

The language supports the early conceptual stages of design with its behavioral level of abstraction, andthe later implementation stages with its structural abstractions. The language includeshierarchical constructs, allowing the designer to control a description’s complexity.Verilog was originally designed in the winter of 1983/84 as a proprietary verification/simulation product.

Later, several other proprietary analysis tools were developedaround the language, including a fault simulator and a timing analyzer. More recently,Verilog has also provided the input specification for logic and behavioral synthesistools. The Verilog language has been instrumental in providing consistency acrossthese tools. The language was originally standardized as IEEE standard #1364-1995.It has recently been revised and standardized as IEEE standard #1364-2001. Thisbook presents this latest revision of the language, providing material for the beginningstudent and advanced user of the language.It is sometimes difficult to separate the language from the simulator tool becausethe dynamic aspects of the language are defined by the way the simulator works.

Further, it is difficult to separate it from a synthesis tool because the semantics of the language become limited by what a synthesis tool allows in its input specification andproduces as an implementation. Where possible, we have stayed away from simulatorand synthesis-specific details and concentrated on design specification. But, we haveincluded enough information to be able to write working executable models.The Verilog Hardware Description LanguagexviThe book takes a tutorial approach to presenting the language. Indeed, we startwith a tutorial introduction that presents, via examples, the major features of the language and the prevalent styles of describing systems. We follow this with a detailedpresentation on using the language for synthesizing combinational and sequential systems.

We then continue with a more complete discussion of the language constructs.Our approach is to provide a means of learning by observing the examples anddoing exercises. Numerous examples are provided to allow the reader to learn (and relearn!) easily by example. It is strongly recommended that you try the exercises asearly as possible with the aid of a Verilog simulator. The examples shown in the bookare available in electronic form on the enclosed CD. Also included on the CD is asimulator. The simulator is limited in the size of description it will handle.The majority of the book assumes a knowledge of introductory logic design andsoftware programming. As such, the book is of use to practicing integrated circuitdesign engineers, and undergraduate and graduate electrical or computer engineeringstudents.

The tutorial introduction is organized in a manner appropriate for use witha course in introductory logic design. A separate appendix, keyed into the tutorialintroduction, provides solved exercises that discuss common errors. The book has alsobeen used for courses in introductory and upper level logic and integrated circuitdesign, computer architecture, and computer-aided design (CAD). It provides complete coverage of the language for design courses, and how a simulator works forCAD courses. For those familiar with the language, we provide a preface that coversmost of the new additions to the 2001 language standard.The book is organized into eleven chapters and eight appendices.