ATmega8 (961722), страница 9
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When the bandgap reference is connected to the Analog Comparator (by settingthe ACBG bit in ACSR).3. When the ADC is enabled.Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, theuser must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the usercan avoid the three conditions above to ensure that the reference is turned off beforeentering Power-down mode.Table 16. Internal Voltage Reference CharacteristicsSymbol40ParameterMinTypMaxUnitsVBGBandgap reference voltage1.151.231.40VtBGBandgap reference start-up time4070µsIBGBandgap reference current consumption10µAATmega8(L)2486O–AVR–10/04ATmega8(L)Watchdog TimerThe Watchdog Timer is clocked from a separate On-chip Oscillator which runs at1 MHz.
This is the typical value at VCC = 5V. See characterization data for typical valuesat other VCC levels. By controlling the Watchdog Timer prescaler, the Watchdog Resetinterval can be adjusted as shown in Table 17 on page 42. The WDR – Watchdog Reset– instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it isdisabled and when a Chip Reset occurs. Eight different clock cycle periods can beselected to determine the reset period.
If the reset period expires without anotherWatchdog Reset, the ATmega8 resets and executes from the Reset Vector. For timingdetails on the Watchdog Reset, refer to page 39.To prevent unintentional disabling of the Watchdog, a special turn-off sequence must befollowed when the Watchdog is disabled. Refer to the description of the Watchdog TimerControl Register for details.Figure 20. Watchdog TimerWATCHDOGOSCILLATORWatchdog Timer ControlRegister – WDTCRBit76543210–––WDCEWDEWDP2WDP1WDP0Read/WriteRRRR/WR/WR/WR/WR/WInitial Value00000000WDTCR• Bits 7..5 – Res: Reserved BitsThese bits are reserved bits in the ATmega8 and will always read as zero.• Bit 4 – WDCE: Watchdog Change EnableThis bit must be set when the WDE bit is written to logic zero.
Otherwise, the Watchdogwill not be disabled. Once written to one, hardware will clear this bit after four clockcycles. Refer to the description of the WDE bit for a Watchdog disable procedure. InSafety Level 1 and 2, this bit must also be set when changing the prescaler bits. See theCode Examples on page 43.412486O–AVR–10/04• Bit 3 – WDE: Watchdog EnableWhen the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE iswritten to logic zero, the Watchdog Timer function is disabled.
WDE can only be clearedif the WDCE bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be followed:1. In the same operation, write a logic one to WDCE and WDE. A logic one must bewritten to WDE even though it is set to one before the disable operation starts.2. Within the next four clock cycles, write a logic 0 to WDE. This disables theWatchdog.• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when theWatchdog Timer is enabled.
The different prescaling values and their correspondingTimeout Periods are shown in Table 17.Table 17. Watchdog Timer Prescale SelectWDP2WDP1WDP0Number of WDTOscillator CyclesTypical Time-outat VCC = 3.0VTypical Time-outat VCC = 5.0V00016K (16,384)17.1 ms16.3 ms00132K (32,768)34.3 ms32.5 ms01064K (65,536)68.5 ms65 ms011128K (131,072)0.14 s0.13 s100256K (262,144)0.27 s0.26 s101512K (524,288)0.55 s0.52 s1101,024K (1,048,576)1.1 s1.0 s1112,048K (2,097,152)2.2 s2.1 sThe following code example shows one assembly and one C function for turning off theWDT.
The example assumes that interrupts are controlled (for example, by disablinginterrupts globally) so that no interrupts will occur during execution of these functions.42ATmega8(L)2486O–AVR–10/04ATmega8(L)Timed Sequences forChanging theConfiguration of theWatchdog TimerThe sequence for changing the Watchdog Timer configuration differs slightly betweenthe safety levels. Separate procedures are described for each level.Assembly Code ExampleWDT_off:; reset WDTWDR; Write logical one to WDCE and WDEinr16, WDTCRori r16, (1<<WDCE)|(1<<WDE)out WDTCR, r16; Turn off WDTldi r16, (0<<WDE)out WDTCR, r16retC Code Examplevoid WDT_off(void){/* reset WDT */_WDR();/* Write logical one to WDCE and WDE */WDTCR |= (1<<WDCE) | (1<<WDE);/* Turn off WDT */WDTCR = 0x00;}Safety Level 1 (WDTON FuseUnprogrammed)In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing theWDE bit to 1 without any restriction.
A timed sequence is needed when changing theWatchdog Time-out period or disabling an enabled Watchdog Timer. To disable anenabled Watchdog Timer and/or changing the Watchdog Time-out, the following procedure must be followed:1. In the same operation, write a logic one to WDCE and WDE.
A logic one must bewritten to WDE regardless of the previous value of the WDE bit.2. Within the next four clock cycles, in the same operation, write the WDE and WDPbits as desired, but with the WDCE bit cleared.Safety Level 2 (WDTON FuseProgrammed)In this mode, the Watchdog Timer is always enabled, and the WDE bit will always readas one. A timed sequence is needed when changing the Watchdog Time-out period.
Tochange the Watchdog Time-out, the following procedure must be followed:1. In the same operation, write a logical one to WDCE and WDE. Even though theWDE always is set, the WDE must be written to one to start the timed sequence.Within the next four clock cycles, in the same operation, write the WDP bits as desired,but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.432486O–AVR–10/04InterruptsInterrupt Vectors inATmega8This section describes the specifics of the interrupt handling performed by theATmega8. For a general explanation of the AVR interrupt handling, refer to “Reset andInterrupt Handling” on page 12.Table 18.
Reset and Interrupt VectorsVector No.1ProgramAddress(2)0x000(1)SourceInterrupt DefinitionRESETExternal Pin, Power-on Reset, Brown-outReset, and Watchdog Reset20x001INT0External Interrupt Request 030x002INT1External Interrupt Request 140x003TIMER2 COMPTimer/Counter2 Compare Match50x004TIMER2 OVFTimer/Counter2 Overflow60x005TIMER1 CAPTTimer/Counter1 Capture Event70x006TIMER1 COMPATimer/Counter1 Compare Match A80x007TIMER1 COMPBTimer/Counter1 Compare Match B90x008TIMER1 OVFTimer/Counter1 Overflow100x009TIMER0 OVFTimer/Counter0 Overflow110x00ASPI, STCSerial Transfer Complete120x00BUSART, RXCUSART, Rx Complete130x00CUSART, UDREUSART Data Register Empty140x00DUSART, TXCUSART, Tx Complete150x00EADCADC Conversion Complete160x00FEE_RDYEEPROM Ready170x010ANA_COMPAnalog Comparator180x011TWITwo-wire Serial Interface190x012SPM_RDYStore Program Memory ReadyNotes:1.
When the BOOTRST Fuse is programmed, the device will jump to the Boot Loaderaddress at reset, see “Boot Loader Support – Read-While-Write Self-Programming”on page 206.2. When the IVSEL bit in GICR is set, Interrupt Vectors will be moved to the start of theboot Flash section. The address of each Interrupt Vector will then be the address inthis table added to the start address of the boot Flash section.Table 19 shows reset and Interrupt Vectors placement for the various combinations ofBOOTRST and IVSEL settings.
If the program never enables an interrupt source, theInterrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while theInterrupt Vectors are in the boot section or vice versa.44ATmega8(L)2486O–AVR–10/04ATmega8(L)Table 19. Reset and Interrupt Vectors PlacementBOOTRST(1)IVSEL1Reset AddressInterrupt Vectors Start Address00x0000x001110x000Boot Reset Address + 0x00100Boot Reset Address0x00101Boot Reset AddressBoot Reset Address + 0x001Note:1. The Boot Reset Address is shown in Table 82 on page 217. For the BOOTRST Fuse“1” means unprogrammed while “0” means programmed.The most typical and general program setup for the Reset and Interrupt VectorAddresses in ATmega8 is:addressLabels CodeComments$000rjmpRESET; Reset Handler$001rjmpEXT_INT0; IRQ0 Handler$002rjmpEXT_INT1; IRQ1 Handler$003rjmpTIM2_COMP; Timer2 Compare Handler$004rjmpTIM2_OVF; Timer2 Overflow Handler$005rjmpTIM1_CAPT; Timer1 Capture Handler$006rjmpTIM1_COMPA; Timer1 CompareA Handler$007rjmpTIM1_COMPB; Timer1 CompareB Handler$008rjmpTIM1_OVF; Timer1 Overflow Handler$009rjmpTIM0_OVF; Timer0 Overflow Handler$00arjmpSPI_STC; SPI Transfer Complete Handler$00brjmpUSART_RXC; USART RX Complete Handler$00crjmpUSART_UDRE; UDR Empty Handler$00drjmpUSART_TXC; USART TX Complete Handler$00erjmpADC; ADC Conversion Complete Handler$00frjmpEE_RDY; EEPROM Ready Handler$010rjmpANA_COMP; Analog Comparator Handler$011HandlerrjmpTWSI; Two-wire Serial Interface$012HandlerrjmpSPM_RDY; Store Program Memory Ready;$013RESET: ldi$014outSPH,r16r16,high(RAMEND); Main program start$015ldir16,low(RAMEND)$016outSPL,r16$017sei$018<instr>......; Set Stack Pointer to top of RAM; Enable interruptsxxx...452486O–AVR–10/04When the BOOTRST Fuse is unprogrammed, the boot section size set to 2K bytes andthe IVSEL bit in the GICR Register is set before any interrupts are enabled, the mosttypical and general program setup for the Reset and Interrupt Vector Addresses is:AddressLabels Code$000;$001rjmpRESET:ldiCommentsRESET; Reset handlerr16,high(RAMEND); Main program start$002outSPH,r16; Set Stack Pointer to top of RAM$003ldir16,low(RAMEND)$004outSPL,r16$005sei$006<instr>; Enable interruptsxxx;.org $c01$c01rjmpEXT_INT0; IRQ0 Handler$c02rjmpEXT_INT1; IRQ1 Handler.........
;$c12HandlerrjmpSPM_RDY; Store Program Memory ReadyWhen the BOOTRST Fuse is programmed and the boot section size set to 2K bytes, themost typical and general program setup for the Reset and Interrupt Vector Addresses is:AddressLabels CodeComments.org $001$001rjmpEXT_INT0; IRQ0 Handler$002rjmpEXT_INT1; IRQ1 Handler.........;$012HandlerrjmpSPM_RDY; Store Program Memory ReadyrjmpRESET; Reset handler;.org $c00$c00;$c0146RESET:ldir16,high(RAMEND); Main program start$c02outSPH,r16; Set Stack Pointer to top of RAM$c03ldir16,low(RAMEND)$c04outSPL,r16$c05sei$c06<instr>; Enable interruptsxxxATmega8(L)2486O–AVR–10/04ATmega8(L)When the BOOTRST Fuse is programmed, the boot section size set to 2K bytes, andthe IVSEL bit in the GICR Register is set before any interrupts are enabled, the mosttypical and general program setup for the Reset and Interrupt Vector Addresses is:AddressLabelsCodeComments;Moving Interrupts BetweenApplication and Boot SpaceGeneral Interrupt ControlRegister – GICR.org $c00$c00$c01rjmprjmpRESETEXT_INT0; Reset handler; IRQ0 Handler$c02rjmpEXT_INT1; IRQ1 Handler.........
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