ATmega8 (961722), страница 13
Текст из файла (страница 13)
Note that recognition of falling or rising edge interrupts on INT0 and INT1requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on page 23. Low level interrupts on INT0/INT1 are detected asynchronously. Thisimplies that these interrupts can be used for waking the part also from sleep modesother than Idle mode.
The I/O clock is halted in all sleep modes except Idle mode.Note that if a level triggered interrupt is used for wake-up from Power-down mode, thechanged level must be held for some time to wake up the MCU. This makes the MCUless sensitive to noise. The changed level is sampled twice by the Watchdog Oscillatorclock. The period of the Watchdog Oscillator is 1 µs (nominal) at 5.0V and 25°C. Thefrequency of the Watchdog Oscillator is voltage dependent as shown in “Electrical Characteristics” on page 239.
The MCU will wake up if the input has the required level duringthis sampling or if it is held until the end of the start-up time. The start-up time is definedby the SUT Fuses as described in “System Clock and Clock Options” on page 23. If thelevel is sampled twice by the Watchdog Oscillator clock but disappears before the endof the start-up time, the MCU will still wake up, but no interrupt will be generated. Therequired level must be held long enough for the MCU to complete the wake up to triggerthe level interrupt.MCU Control Register –MCUCRThe MCU Control Register contains control bits for interrupt sense control and generalMCU functions.Bit76543210SESM2SM1SM0ISC11ISC10ISC01ISC00Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000MCUCR• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0The External Interrupt 1 is activated by the external pin INT1 if the SREG I-bit and thecorresponding interrupt mask in the GICR are set.
The level and edges on the externalINT1 pin that activate the interrupt are defined in Table 31. The value on the INT1 pin issampled before detecting edges. If edge or toggle interrupt is selected, pulses that lastlonger than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
If low level interrupt is selected, the low level must be helduntil the completion of the currently executing instruction to generate an interrupt.Table 31. Interrupt 1 Sense Control64ISC11ISC10Description00The low level of INT1 generates an interrupt request.01Any logical change on INT1 generates an interrupt request.10The falling edge of INT1 generates an interrupt request.11The rising edge of INT1 generates an interrupt request.ATmega8(L)2486O–AVR–10/04ATmega8(L)• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and thecorresponding interrupt mask are set. The level and edges on the external INT0 pin thatactivate the interrupt are defined in Table 32.
The value on the INT0 pin is sampledbefore detecting edges. If edge or toggle interrupt is selected, pulses that last longerthan one clock period will generate an interrupt. Shorter pulses are not guaranteed togenerate an interrupt. If low level interrupt is selected, the low level must be held untilthe completion of the currently executing instruction to generate an interrupt.Table 32. Interrupt 0 Sense ControlGeneral Interrupt ControlRegister – GICRISC01ISC0000The low level of INT0 generates an interrupt request.01Any logical change on INT0 generates an interrupt request.10The falling edge of INT0 generates an interrupt request.11The rising edge of INT0 generates an interrupt request.BitDescription76543210INT1INT0––––IVSELIVCERead/WriteR/WR/WRRRRR/WR/WInitial Value00000000GICR• Bit 7 – INT1: External Interrupt Request 1 EnableWhen the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),the external pin interrupt is enabled.
The Interrupt Sense Control1 bits 1/0 (ISC11 andISC10) in the MCU general Control Register (MCUCR) define whether the externalinterrupt is activated on rising and/or falling edge of the INT1 pin or level sensed. Activityon the pin will cause an interrupt request even if INT1 is configured as an output. Thecorresponding interrupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector.• Bit 6 – INT0: External Interrupt Request 0 EnableWhen the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 andISC00) in the MCU general Control Register (MCUCR) define whether the externalinterrupt is activated on rising and/or falling edge of the INT0 pin or level sensed.
Activityon the pin will cause an interrupt request even if INT0 is configured as an output. Thecorresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.652486O–AVR–10/04General Interrupt FlagRegister – GIFRBit7654321INTF1INTF0–––––0–Read/WriteR/WR/WRRRRRRInitial Value00000000GIFR• Bit 7 – INTF1: External Interrupt Flag 1When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one).If the I-bit in SREG and the INT1 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector.
The flag is cleared when the interrupt routine is executed.Alternatively, the flag can be cleared by writing a logical one to it. This flag is alwayscleared when INT1 is configured as a level interrupt.• Bit 6 – INTF0: External Interrupt Flag 0When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).If the I-bit in SREG and the INT0 bit in GICR are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.Alternatively, the flag can be cleared by writing a logical one to it. This flag is alwayscleared when INT0 is configured as a level interrupt.66ATmega8(L)2486O–AVR–10/04ATmega8(L)8-bit Timer/Counter0Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module.
Themain features are:• Single Channel Counter• Frequency Generator• External Event Counter• 10-bit Clock PrescalerOverviewA simplified block diagram of the 8-bit Timer/Counter is shown in Figure 26. For theactual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessibleI/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/ORegister and bit locations are listed in the “8-bit Timer/Counter Register Description” onpage 70.Figure 26.
8-bit Timer/Counter Block DiagramTCCRnDATA BUScountTOVn(Int.Req.)Control LogicClock SelectEdgeDetectorTimer/CounterTCNTnRegistersclkTnTn( From Prescaler )= 0xFFThe Timer/Counter (TCNT0) is an 8-bit register. Interrupt request (abbreviated toInt. Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR).All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK).TIFR and TIMSK are not shown in the figure since these registers are shared by othertimer units.The Timer/Counter can be clocked internally or via the prescaler, or by an external clocksource on the T0 pin. The Clock Select logic block controls which clock source and edgethe Timer/Counter uses to increment its value.
The Timer/Counter is inactive when noclock source is selected. The output from the clock select logic is referred to as the timerclock (clkT0).DefinitionsMany register and bit references in this document are written in general form. A lowercase “n” replaces the Timer/Counter number, in this case 0. However, when using theregister or bit defines in a program, the precise form must be used i.e. TCNT0 foraccessing Timer/Counter0 counter value and so on.The definitions in Table 33 are also used extensively throughout this datasheet.Table 33.
DefinitionsBOTTOMThe counter reaches the BOTTOM when it becomes 0x00MAXThe counter reaches its MAXimum when it becomes 0xFF (decimal 255)672486O–AVR–10/04Timer/Counter ClockSourcesThe Timer/Counter can be clocked by an internal or an external clock source. The clocksource is selected by the clock select logic which is controlled by the clock select(CS02:0) bits located in the Timer/Counter Control Register (TCCR0). For details onclock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” onpage 72.Counter UnitThe main part of the 8-bit Timer/Counter is the programmable counter unit.
Figure 27shows a block diagram of the counter and its surroundings.Figure 27. Counter Unit Block DiagramTOVn(Int. Req.)DATA BUSClock SelectTCNTncountControl LogicmaxclkTnEdgeDetectorTn( From Prescaler )Signal description (internal signals):countIncrement TCNT0 by 1.clkTnTimer/Counter clock, referred to as clkT0 in the following.maxSignalize that TCNT0 has reached maximum value.The counter is incremented at each timer clock (clkT0). clkT0 can be generated from anexternal or internal clock source, selected by the clock select bits (CS02:0). When noclock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 valuecan be accessed by the CPU, regardless of whether clkT0 is present or not.
A CPU writeoverrides (has priority over) all counter clear or count operations.Operation68The counting direction is always up (incrementing), and no counter clear is performed.The counter simply overruns when it passes its maximum 8-bit value (MAX = 0xFF) andthen restarts from the bottom (0x00).
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
