ATmega8 (961722), страница 17
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Then when the Low byte (OCR1xL) is written to the lower eight bits, the High bytewill be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle.For more information of how to access the 16-bit registers refer to “Accessing 16-bitRegisters” on page 77.Force Output CompareIn non-PWM Waveform Generation modes, the match output of the comparator can beforced by writing a one to the Force Output Compare (FOC1x) bit. Forcing CompareMatch will not set the OCF1x Flag or reload/clear the timer, but the OC1x pin will beupdated as if a real Compare Match had occurred (the COM1x1:0 bits settings definewhether the OC1x pin is set, cleared or toggled).Compare Match Blocking byTCNT1 WriteAll CPU writes to the TCNT1 Register will block any Compare Match that occurs in thenext timer clock cycle, even when the timer is stopped.
This feature allows OCR1x to beinitialized to the same value as TCNT1 without triggering an interrupt when theTimer/Counter clock is enabled.Using the Output CompareUnitSince writing TCNT1 in any mode of operation will block all compare matches for onetimer clock cycle, there are risks involved when changing TCNT1 when using any of theOutput Compare channels, independent of whether the Timer/Counter is running or not.If the value written to TCNT1 equals the OCR1x value, the Compare Match will bemissed, resulting in incorrect waveform generation. Do not write the TCNT1 equal toTOP in PWM modes with variable TOP values. The Compare Match for the TOP will beignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNT1 valueequal to BOTTOM when the counter is downcounting.The setup of the OC1x should be performed before setting the Data Direction Registerfor the port pin to output. The easiest way of setting the OC1x value is to use the ForceOutput Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps itsvalue even when changing between Waveform Generation modes.Be aware that the COM1x1:0 bits are not double buffered together with the comparevalue. Changing the COM1x1:0 bits will take effect immediately.84ATmega8(L)2486O–AVR–10/04ATmega8(L)Compare Match OutputUnitThe Compare Output mode (COM1x1:0) bits have two functions.
The waveform generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the nextCompare Match. Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 36 shows a simplified schematic of the logic affected by the COM1x1:0 bit setting.The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold.
Only the parts ofthe general I/O Port Control Registers (DDR and PORT) that are affected by theCOM1x1:0 bits are shown. When referring to the OC1x state, the reference is for theinternal OC1x Register, not the OC1x pin. If a System Reset occur, the OC1x Register isreset to “0”.Figure 36. Compare Match Output Unit, SchematicCOMnx1COMnx0FOCnxWaveformGeneratorDQ1OCnxDATABUSD0OCnxPinQPORTDQDDRclk I/OThe general I/O port function is overridden by the Output Compare (OC1x) from thewaveform generator if either of the COM1x1:0 bits are set. However, the OC1x pindirection (input or output) is still controlled by the Data Direction Register (DDR) for theport pin.
The Data Direction Register bit for the OC1x pin (DDR_OC1x) must be set asoutput before the OC1x value is visible on the pin. The port override function is generallyindependent of the Waveform Generation mode, but there are some exceptions. Referto Table 36, Table 37 and Table 38 for details.The design of the Output Compare Pin logic allows initialization of the OC1x statebefore the output is enabled. Note that some COM1x1:0 bit settings are reserved forcertain modes of operation.
See “16-bit Timer/Counter Register Description” on page95.The COM1x1:0 bits have no effect on the Input Capture unit.852486O–AVR–10/04Compare Output Mode andWaveform GenerationThe waveform generator uses the COM1x1:0 bits differently in normal, CTC, and PWMmodes. For all modes, setting the COM1x1:0 = 0 tells the waveform generator that noaction on the OC1x Register is to be performed on the next Compare Match.
For compare output actions in the non-PWM modes refer to Table 36 on page 95. For fast PWMmode refer to Table 37 on page 96, and for phase correct and phase and frequency correct PWM refer to Table 38 on page 96.A change of the COM1x1:0 bits state will have effect at the first Compare Match afterthe bits are written. For non-PWM modes, the action can be forced to have immediateeffect by using the FOC1x strobe bits.Modes of OperationThe mode of operation (i.e., the behavior of the Timer/Counter and the Output Comparepins) is defined by the combination of the Waveform Generation mode (WGM13:0) andCompare Output mode (COM1x1:0) bits. The Compare Output mode bits do not affectthe counting sequence, while the Waveform Generation mode bits do.
The COM1x1:0bits control whether the PWM output generated should be inverted or not (inverted ornon-inverted PWM). For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared or toggle at a Compare Match. See “Compare Match OutputUnit” on page 85.For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 93.Normal ModeThe simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode thecounting direction is always up (incrementing), and no counter clear is performed.
Thecounter simply overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) andthen restarts from the BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in the same timer clock cycle as the TCNT1 becomes zero.The TOV1 Flag in this case behaves like a 17th bit, except that it is only set, not cleared.However, combined with the timer overflow interrupt that automatically clears the TOV1Flag, the timer resolution can be increased by software. There are no special cases toconsider in the Normal mode, a new counter value can be written anytime.The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval between the external events must not exceed the resolution of the counter.If the interval between events are too long, the timer overflow interrupt or the prescalermust be used to extend the resolution for the capture unit.The Output Compare units can be used to generate interrupts at some given time.
Usingthe Output Compare to generate waveforms in Normal mode is not recommended,since this will occupy too much of the CPU time.Clear Timer on CompareMatch (CTC) ModeIn Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1Register are used to manipulate the counter resolution. In CTC mode the counter iscleared to zero when the counter value (TCNT1) matches either the OCR1A (WGM13:0= 4) or the ICR1 (WGM13:0 = 12). The OCR1A or ICR1 define the top value for thecounter, hence also its resolution. This mode allows greater control of the CompareMatch output frequency.
It also simplifies the operation of counting external events.The timing diagram for the CTC mode is shown in Figure 37. The counter value(TCNT1) increases until a Compare Match occurs with either OCR1A or ICR1, and thencounter (TCNT1) is cleared.86ATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 37. CTC Mode, Timing DiagramOCnA Interrupt Flag Setor ICFn Interrupt Flag Set(Interrupt on TOP)TCNTnOCnA(Toggle)Period(COMnA1:0 = 1)1234An interrupt can be generated at each time the counter value reaches the TOP value byeither using the OCF1A or ICF1 Flag according to the register used to define the TOPvalue.
If the interrupt is enabled, the interrupt handler routine can be used for updatingthe TOP value. However, changing the TOP to a value close to BOTTOM when thecounter is running with none or a low prescaler value must be done with care since theCTC mode does not have the double buffering feature. If the new value written toOCR1A or ICR1 is lower than the current value of TCNT1, the counter will miss theCompare Match. The counter will then have to count to its maximum value (0xFFFF)and wrap around starting at 0x0000 before the Compare Match can occur.
In manycases this feature is not desirable. An alternative will then be to use the fast PWM modeusing OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be doublebuffered.For generating a waveform output in CTC mode, the OC1A output can be set to toggleits logical level on each Compare Match by setting the Compare Output mode bits totoggle mode (COM1A1:0 = 1). The OC1A value will not be visible on the port pin unlessthe data direction for the pin is set to output (DDR_OC1A = 1). The waveform generatedwill have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000).The waveform frequency is defined by the following equation:f clk_I/Of OCnA = -------------------------------------------------2 ⋅ N ⋅ ( 1 + OCRnA )The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cyclethat the counter counts from MAX to 0x0000.Fast PWM ModeThe fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a high frequency PWM waveform generation option.
The fast PWM differs fromthe other PWM options by its single-slope operation. The counter counts from BOTTOMto TOP then restarts from BOTTOM. In non-inverting Compare Output mode, the OutputCompare (OC1x) is set on the Compare Match between TCNT1 and OCR1x, andcleared at TOP. In inverting Compare Output mode output is cleared on Compare Matchand set at TOP. Due to the single-slope operation, the operating frequency of the fastPWM mode can be twice as high as the phase correct and phase and frequency correctPWM modes that use dual-slope operation. This high frequency makes the fast PWMmode well suited for power regulation, rectification, and DAC applications.
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