ATmega8 (961722), страница 20
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Table 36 shows the COM1x1:0 bit functionalitywhen the WGM13:0 bits are set to a normal or a CTC mode (non-PWM).Table 36. Compare Output Mode, Non-PWMCOM1A1/COM1B1COM1A0/COM1B000Normal port operation, OC1A/OC1B disconnected.01Toggle OC1A/OC1B on Compare Match10Clear OC1A/OC1B on Compare Match (Set output to low level)11Set OC1A/OC1B on Compare Match (Set output to high level)Description952486O–AVR–10/04Table 37 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to thefast PWM mode.Table 37.
Compare Output Mode, Fast PWM(1)COM1A1/COM1B1COM1A0/COM1B000Normal port operation, OC1A/OC1B disconnected.01WGM13:0 = 15: Toggle OC1A on Compare Match, OC1Bdisconnected (normal port operation). For all other WGM1settings, normal port operation, OC1A/OC1B disconnected.10Clear OC1A/OC1B on Compare Match, set OC1A/OC1B at TOP11Set OC1A/OC1B on Compare Match, clear OC1A/OC1B at TOPNote:Description1.
A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 isset. In this case the Compare Match is ignored, but the set or clear is done at TOP.See “Fast PWM Mode” on page 87. for more details.Table 38 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to thephase correct or the phase and frequency correct, PWM mode.Table 38. Compare Output Mode, Phase Correct and Phase and Frequency CorrectPWM(1)COM1A1/COM1B1COM1A0/COM1B000Normal port operation, OC1A/OC1B disconnected.01WGM13:0 = 9 or 14: Toggle OC1A on Compare Match, OC1Bdisconnected (normal port operation).
For all other WGM1settings, normal port operation, OC1A/OC1B disconnected.10Clear OC1A/OC1B on Compare Match when up-counting. SetOC1A/OC1B on Compare Match when downcounting.11Set OC1A/OC1B on Compare Match when up-counting. ClearOC1A/OC1B on Compare Match when downcounting.Note:Description1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 isset.
See “Phase Correct PWM Mode” on page 89. for more details.• Bit 3 – FOC1A: Force Output Compare for channel A• Bit 2 – FOC1B: Force Output Compare for channel BThe FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWMmode. However, for ensuring compatibility with future devices, these bits must be set tozero when TCCR1A is written when operating in a PWM mode.
When writing a logicalone to the FOC1A/FOC1B bit, an immediate Compare Match is forced on the waveformgeneration unit. The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the FOC1A/FOC1B bits are implemented as strobes. Therefore it is thevalue present in the COM1x1:0 bits that determine the effect of the forced compare.A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in ClearTimer on Compare Match (CTC) mode using OCR1A as TOP.The FOC1A/FOC1B bits are always read as zero.• Bit 1:0 – WGM11:0: Waveform Generation ModeCombined with the WGM13:2 bits found in the TCCR1B Register, these bits control thecounting sequence of the counter, the source for maximum (TOP) counter value, and96ATmega8(L)2486O–AVR–10/04ATmega8(L)what type of waveform generation to be used, see Table 39.
Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on CompareMatch (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See“Modes of Operation” on page 86.)Table 39. Waveform Generation Mode Bit DescriptionModeWGM13WGM12(CTC1)WGM11(PWM11)WGM10(PWM10)Timer/Counter Mode ofOperation(1)TOPUpdate ofOCR1xTOV1 FlagSet on00000Normal0xFFFFImmediateMAX10001PWM, Phase Correct, 8-bit0x00FFTOPBOTTOM20010PWM, Phase Correct, 9-bit0x01FFTOPBOTTOM30011PWM, Phase Correct, 10-bit0x03FFTOPBOTTOM40100CTCOCR1AImmediateMAX50101Fast PWM, 8-bit0x00FFTOPTOP60110Fast PWM, 9-bit0x01FFTOPTOP70111Fast PWM, 10-bit0x03FFTOPTOP81000PWM, Phase and Frequency CorrectICR1BOTTOMBOTTOM91001PWM, Phase and Frequency CorrectOCR1ABOTTOMBOTTOM101010PWM, Phase CorrectICR1TOPBOTTOM111011PWM, Phase CorrectOCR1ATOPBOTTOM121100CTCICR1ImmediateMAX131101(Reserved)–––141110Fast PWMICR1TOPTOP151111Fast PWMOCR1ATOPTOPNote:1.
The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality andlocation of these bits are compatible with previous versions of the timer.972486O–AVR–10/04Timer/Counter 1 ControlRegister B – TCCR1BBit76543210ICNC1ICES1–WGM13WGM12CS12CS11CS10Read/WriteR/WR/WRR/WR/WR/WR/WR/WInitial Value00000000TCCR1B• Bit 7 – ICNC1: Input Capture Noise CancelerSetting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is activated, the input from the Input Capture Pin (ICP1) is filtered.
The filterfunction requires four successive equal valued samples of the ICP1 pin for changing itsoutput. The Input Capture is therefore delayed by four Oscillator cycles when the noisecanceler is enabled.• Bit 6 – ICES1: Input Capture Edge SelectThis bit selects which edge on the Input Capture Pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used astrigger, and when the ICES1 bit is written to one, a rising (positive) edge will trigger thecapture.When a capture is triggered according to the ICES1 setting, the counter value is copiedinto the Input Capture Register (ICR1).
The event will also set the Input Capture Flag(ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt isenabled.When the ICR1 is used as TOP value (see description of the WGM13:0 bits located inthe TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequentlythe Input Capture function is disabled.• Bit 5 – Reserved BitThis bit is reserved for future use.
For ensuring compatibility with future devices, this bitmust be written to zero when TCCR1B is written.• Bit 4:3 – WGM13:2: Waveform Generation ModeSee TCCR1A Register description.• Bit 2:0 – CS12:0: Clock SelectThe three clock select bits select the clock source to be used by the Timer/Counter, seeFigure 41 and Figure 42.Table 40.
Clock Select Bit Description98CS12CS11CS10Description000No clock source. (Timer/Counter stopped)001clkI/O/1 (No prescaling)010clkI/O/8 (From prescaler)011clkI/O/64 (From prescaler)100clkI/O/256 (From prescaler)101clkI/O/1024 (From prescaler)110External clock source on T1 pin. Clock on falling edge.111External clock source on T1 pin. Clock on rising edge.ATmega8(L)2486O–AVR–10/04ATmega8(L)If external pin modes are used for the Timer/Counter1, transitions on the T1 pin willclock the counter even if the pin is configured as an output. This feature allows softwarecontrol of the counting.Timer/Counter 1 – TCNT1Hand TCNT1LBit76543210TCNT1[15:8]TCNT1HTCNT1[7:0]TCNT1LRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) givedirect access, both for read and for write operations, to the Timer/Counter unit 16-bitcounter.
To ensure that both the high and Low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bittemporary High byte Register (TEMP). This temporary register is shared by all the other16-bit registers. See “Accessing 16-bit Registers” on page 77.Modifying the counter (TCNT1) while the counter is running introduces a risk of missinga Compare Match between TCNT1 and one of the OCR1x Registers.Writing to the TCNT1 Register blocks (removes) the Compare Match on the followingtimer clock for all compare units.Output Compare Register 1 A– OCR1AH and OCR1ALBit76543210OCR1A[15:8]OCR1AHOCR1A[7:0]Output Compare Register 1 B– OCR1BH and OCR1BLOCR1ALRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210OCR1B[15:8]OCR1BHOCR1B[7:0]OCR1BLRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000The Output Compare Registers contain a 16-bit value that is continuously comparedwith the counter value (TCNT1).
A match can be used to generate an Output CompareInterrupt, or to generate a waveform output on the OC1x pin.The Output Compare Registers are 16-bit in size. To ensure that both the high and Lowbytes are written simultaneously when the CPU writes to these registers, the access isperformed using an 8-bit temporary High byte Register (TEMP). This temporary registeris shared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 77.992486O–AVR–10/04Input Capture Register 1 –ICR1H and ICR1LBit76543210ICR1[15:8]ICR1HICR1[7:0]ICR1LRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000The Input Capture is updated with the counter (TCNT1) value each time an event occurson the ICP1 pin (or optionally on the Analog Comparator Output for Timer/Counter1).The Input Capture can be used for defining the counter TOP value.The Input Capture Register is 16-bit in size.
To ensure that both the high and Low bytesare read simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary High byte Register (TEMP). This temporary register isshared by all the other 16-bit registers. See “Accessing 16-bit Registers” on page 77.Timer/Counter Interrupt MaskRegister – TIMSK(1)Bit76543210OCIE2TOIE2TICIE1OCIE1AOCIE1BTOIE1–TOIE0Read/WriteR/WR/WR/WR/WR/WR/WRR/WInitial Value00000000Note:TIMSK1. This register contains interrupt control bits for several Timer/Counters, but onlyTimer1 bits are described in this section.
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