ATmega8 (961722), страница 16
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When no clock sourceis selected (CS12:0 = 0) the timer is stopped. However, the TCNT1 value can beaccessed by the CPU, independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.80ATmega8(L)2486O–AVR–10/04ATmega8(L)The counting sequence is determined by the setting of the Waveform Generation modebits (WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A andTCCR1B). There are close connections between how the counter behaves (counts) andhow waveforms are generated on the Output Compare Outputs OC1x.
For more detailsabout advanced counting sequences and waveform generation, see “Modes of Operation” on page 86.The Timer/Counter Overflow (TOV1) fLag is set according to the mode of operationselected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.Input Capture UnitThe Timer/Counter incorporates an Input Capture unit that can capture external eventsand give them a time-stamp indicating time of occurrence.
The external signal indicatingan event, or multiple events, can be applied via the ICP1 pin or alternatively, via theAnalog Comparator unit. The time-stamps can then be used to calculate frequency,duty-cycle, and other features of the signal applied. Alternatively the time-stamps can beused for creating a log of the events.The Input Capture unit is illustrated by the block diagram shown in Figure 34. The elements of the block diagram that are not directly a part of the Input Capture unit are grayshaded. The small “n” in register and bit names indicates the Timer/Counter number.Figure 34.
Input Capture Unit Block DiagramDATA BUS(8-bit)TEMP (8-bit)ICRnH (8-bit)WRITEICRnL (8-bit)TCNTnH (8-bit)ICRn (16-bit Register)ACO*AnalogComparatorACIC*TCNTnL (8-bit)TCNTn (16-bit Counter)ICNCICESNoiseCancelerEdgeDetectorICFn (Int. Req.)ICPnWhen a change of the logic level (an event) occurs on the Input Capture Pin (ICP1),alternatively on the Analog Comparator Output (ACO), and this change confirms to thesetting of the edge detector, a capture will be triggered.
When a capture is triggered, the16-bit value of the counter (TCNT1) is written to the Input Capture Register (ICR1). TheInput Capture Flag (ICF1) is set at the same system clock as the TCNT1 value is copiedinto ICR1 Register. If enabled (TICIE1 = 1), the Input Capture Flag generates an InputCapture interrupt. The ICF1 Flag is automatically cleared when the interrupt is executed.Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/Obit location.812486O–AVR–10/04Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading theLow byte (ICR1L) and then the High byte (ICR1H).
When the Low byte is read the Highbyte is copied into the High byte temporary register (TEMP). When the CPU reads theICR1H I/O location it will access the TEMP Register.The ICR1 Register can only be written when using a Waveform Generation mode thatutilizes the ICR1 Register for defining the counter’s TOP value. In these cases theWaveform Generation mode (WGM13:0) bits must be set before the TOP value can bewritten to the ICR1 Register. When writing the ICR1 Register the High byte must be written to the ICR1H I/O location before the Low byte is written to ICR1L.For more information on how to access the 16-bit registers refer to “Accessing 16-bitRegisters” on page 77.Input Capture Pin SourceThe main trigger source for the Input Capture unit is the Input Capture Pin (ICP1).Timer/Counter 1 can alternatively use the Analog Comparator Output as trigger sourcefor the Input Capture unit.
The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Controland Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change.Both the Input Capture Pin (ICP1) and the Analog Comparator Output (ACO) inputs aresampled using the same technique as for the T1 pin (Figure 30 on page 72). The edgedetector is also identical. However, when the noise canceler is enabled, additional logicis inserted before the edge detector, which increases the delay by four system clockcycles.
Note that the input of the noise canceler and edge detector is always enabledunless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 todefine TOP.An Input Capture can be triggered by software by controlling the port of the ICP1 pin.Noise CancelerThe noise canceler improves noise immunity by using a simple digital filtering scheme.The noise canceler input is monitored over four samples, and all four must be equal forchanging the output that in turn is used by the edge detector.The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bitin Timer/Counter Control Register B (TCCR1B).
When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, tothe update of the ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the prescaler.Using the Input Capture UnitThe main challenge when using the Input Capture unit is to assign enough processorcapacity for handling the incoming events.
The time between two events is critical. If theprocessor has not read the captured value in the ICR1 Register before the next eventoccurs, the ICR1 will be overwritten with a new value. In this case the result of the capture will be incorrect.When using the Input Capture interrupt, the ICR1 Register should be read as early in theinterrupt handler routine as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximumnumber of clock cycles it takes to handle any of the other interrupt requests.Using the Input Capture unit in any mode of operation when the TOP value (resolution)is actively changed during operation, is not recommended.Measurement of an external signal’s duty cycle requires that the trigger edge is changedafter each capture.
Changing the edge sensing must be done as early as possible afterthe ICR1 Register has been read. After a change of the edge, the Input Capture Flag82ATmega8(L)2486O–AVR–10/04ATmega8(L)(ICF1) must be cleared by software (writing a logical one to the I/O bit location). Formeasuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupthandler is used).Output Compare UnitsThe 16-bit comparator continuously compares TCNT1 with the Output Compare Register (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will setthe Output Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x =1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x Flagis automatically cleared when the interrupt is executed. Alternatively the OCF1x Flagcan be cleared by software by writing a logical one to its I/O bit location. The waveformgenerator uses the match signal to generate an output according to operating mode setby the Waveform Generation mode (WGM13:0) bits and Compare Output mode(COM1x1:0) bits.
The TOP and BOTTOM signals are used by the waveform generatorfor handling the special cases of the extreme values in some modes of operation (See“Modes of Operation” on page 86.)A special feature of Output Compare unit A allows it to define the Timer/Counter TOPvalue (i.e. counter resolution). In addition to the counter resolution, the TOP valuedefines the period time for waveforms generated by the waveform generator.Figure 35 shows a block diagram of the Output Compare unit.
The small “n” in the register and bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x”indicates Output Compare unit (A/B). The elements of the block diagram that are notdirectly a part of the Output Compare unit are gray shaded.Figure 35. Output Compare Unit, Block DiagramDATA BUS (8-bit)TEMP (8-bit)OCRnxH Buf. (8-bit)OCRnxL Buf. (8-bit)TCNTnH (8-bit)OCRnx Buffer (16-bit Register)OCRnxH (8-bit)TCNTnL (8-bit)TCNTn (16-bit Counter)OCRnxL (8-bit)OCRnx (16-bit Register)= (16-bit Comparator )OCFnx (Int.Req.)TOPBOTTOMWaveform GeneratorWGMn3:0OCnxCOMnx1:0The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes.
For the normal and Clear Timer on Compare (CTC) modes ofoperation, the double buffering is disabled. The double buffering synchronizes the832486O–AVR–10/04update of the OCR1x Compare Register to either TOP or BOTTOM of the countingsequence. The synchronization prevents the occurrence of odd-length, non-symmetricalPWM pulses, thereby making the output glitch-free.The OCR1x Register access may seem complex, but this is not case. When the doublebuffering is enabled, the CPU has access to the OCR1x Buffer Register, and if doublebuffering is disabled the CPU will access the OCR1x directly.
The content of the OCR1x(Buffer or Compare) Register is only changed by a write operation (the Timer/Counterdoes not update this register automatically as the TCNT1 and ICR1 Register). ThereforeOCR1x is not read via the High byte temporary register (TEMP). However, it is a goodpractice to read the Low byte first as when accessing other 16-bit registers. Writing theOCR1x Registers must be done via the TEMP Register since the compare of all 16-bit isdone continuously. The High byte (OCR1xH) has to be written first. When the High byteI/O location is written by the CPU, the TEMP Register will be updated by the value written.
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