ATmega8 (961722), страница 11
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If the ExternalInterrupt Request is not enabled, SLEEP is active also for these pins. SLEEP is alsooverridden by various other alternate functions as described in “Alternate Port Functions” on page 54.If a logic high level (“one”) is present on an Asynchronous External Interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while theexternal interrupt is not enabled, the corresponding External Interrupt Flag will be setwhen resuming from the above mentioned sleep modes, as the clamping in these sleepmodes produces the requested logic change.532486O–AVR–10/04Unconnected pinsIf some pins are unused, it is recommended to ensure that these pins have a definedlevel. Even though most of the digital inputs are disabled in the deep sleep modes asdescribed above, floating inputs should be avoided to reduce current consumption in allother modes where the digital inputs are enabled (Reset, Active mode and Idle mode).The simplest method to ensure a defined level of an unused pin, is to enable the internalpull-up.
In this case, the pull-up will be disabled during reset. If low power consumptionduring reset is important, it is recommended to use an external pull-up or pull-down.Connecting unused pins directly to VCC or GND is not recommended, since this maycause excessive currents if the pin is accidentally configured as an output.Alternate Port FunctionsMost port pins have alternate functions in addition to being general digital I/Os.
Figure25 shows how the port pin control signals from the simplified Figure 22 can be overridden by alternate functions. The overriding signals may not be present in all port pins, butthe figure serves as a generic description applicable to all port pins in the AVR microcontroller family.Figure 25. Alternate Port Functions(1)PUOExnPUOVxn1PUD0DDOExnDDOVxn1Q DDDxn0Q CLRWDxPVOExnRESETDATA BUSRDxPVOVxn1PxnQ0DPORTxnQ CLRDIEOExnWPxDIEOVxnRESET10RRxSLEEPSYNCHRONIZERDSETQDRPxQPINxnLCLRQCLRQclk I/ODIxnAIOxnPUOExn:PUOVxn:DDOExn:DDOVxn:PVOExn:PVOVxn:DIEOExn:DIEOVxn:SLEEP:Note:54Pxn PULL-UP OVERRIDE ENABLEPxn PULL-UP OVERRIDE VALUEPxn DATA DIRECTION OVERRIDE ENABLEPxn DATA DIRECTION OVERRIDE VALUEPxn PORT VALUE OVERRIDE ENABLEPxn PORT VALUE OVERRIDE VALUEPxn DIGITAL INPUT-ENABLE OVERRIDE ENABLEPxn DIGITAL INPUT-ENABLE OVERRIDE VALUESLEEP CONTROLPUD:WDx:RDx:RRx:WPx:RPx:clkI/O:DIxn:AIOxn:PULLUP DISABLEWRITE DDRxREAD DDRxREAD PORTx REGISTERWRITE PORTxREAD PORTx PINI/O CLOCKDIGITAL INPUT PIN n ON PORTxANALOG INPUT/OUTPUT PIN n ON PORTx1.
WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,SLEEP, and PUD are common to all ports. All other signals are unique for each pin.ATmega8(L)2486O–AVR–10/04ATmega8(L)Table 21 summarizes the function of the overriding signals. The pin and port indexesfrom Figure 25 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.Table 21. Generic Description of Overriding Signals for Alternate FunctionsSignal NameFull NameDescriptionPUOEPull-up OverrideEnableIf this signal is set, the pull-up enable is controlled bythe PUOV signal.
If this signal is cleared, the pull-up isenabled when {DDxn, PORTxn, PUD} = 0b010.PUOVPull-up OverrideValueIf PUOE is set, the pull-up is enabled/disabled whenPUOV is set/cleared, regardless of the setting of theDDxn, PORTxn, and PUD Register bits.DDOEData DirectionOverride EnableIf this signal is set, the Output Driver Enable iscontrolled by the DDOV signal. If this signal is cleared,the Output driver is enabled by the DDxn Register bit.DDOVData DirectionOverride ValueIf DDOE is set, the Output Driver is enabled/disabledwhen DDOV is set/cleared, regardless of the setting ofthe DDxn Register bit.PVOEPort ValueOverride EnableIf this signal is set and the Output Driver is enabled,the port value is controlled by the PVOV signal.
IfPVOE is cleared, and the Output Driver is enabled, theport Value is controlled by the PORTxn Register bit.PVOVPort ValueOverride ValueIf PVOE is set, the port value is set to PVOV,regardless of the setting of the PORTxn Register bit.DIEOEDigital Input EnableOverride EnableIf this bit is set, the Digital Input Enable is controlled bythe DIEOV signal. If this signal is cleared, the DigitalInput Enable is determined by MCU-state (Normalmode, sleep modes).DIEOVDigital Input EnableOverride ValueIf DIEOE is set, the Digital Input is enabled/disabledwhen DIEOV is set/cleared, regardless of the MCUstate (Normal mode, sleep modes).DIDigital InputThis is the Digital Input to alternate functions. In thefigure, the signal is connected to the output of theschmitt trigger but before the synchronizer. Unless theDigital Input is used as a clock source, the module withthe alternate function will use its own synchronizer.AIOAnalog Input/outputThis is the Analog Input/output to/from alternatefunctions.
The signal is connected directly to the pad,and can be used bi-directionally.The following subsections shortly describe the alternate functions for each port, andrelate the overriding signals to the alternate function. Refer to the alternate functiondescription for further details.552486O–AVR–10/04Special Function IO Register –SFIORBit76543210ACMEPUDPSR2PSR10Read/WriteRRRRR/WR/WR/WR/WInitial Value00000000SFIOR• Bit 2 – PUD: Pull-up DisableWhen this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxnand PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).See “Configuring the Pin” on page 50 for more details about this feature.Alternate Functions of Port BThe Port B pins with alternate functions are shown in Table 22.Table 22.
Port B Pins Alternate FunctionsPort PinAlternate FunctionsPB7XTAL2 (Chip Clock Oscillator pin 2)TOSC2 (Timer Oscillator pin 2)PB6XTAL1 (Chip Clock Oscillator pin 1 or External clock input)TOSC1 (Timer Oscillator pin 1)PB5SCK (SPI Bus Master clock Input)PB4MISO (SPI Bus Master Input/Slave Output)PB3MOSI (SPI Bus Master Output/Slave Input)OC2 (Timer/Counter2 Output Compare Match Output)PB2SS (SPI Bus Master Slave select)OC1B (Timer/Counter1 Output Compare Match B Output)PB1OC1A (Timer/Counter1 Output Compare Match A Output)PB0ICP1 (Timer/Counter1 Input Capture Pin)The alternate pin configuration is as follows:• XTAL2/TOSC2 – Port B, Bit 7XTAL2: Chip clock Oscillator pin 2.
Used as clock pin for crystal Oscillator or Low-frequency crystal Oscillator. When used as a clock pin, the pin can not be used as an I/Opin.TOSC2: Timer Oscillator pin 2. Used only if internal calibrated RC Oscillator is selectedas chip clock source, and the asynchronous timer is enabled by the correct setting inASSR.
When the AS2 bit in ASSR is set (one) to enable asynchronous clocking ofTimer/Counter2, pin PB7 is disconnected from the port, and becomes the inverting output of the Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin,and the pin cannot be used as an I/O pin.If PB7 is used as a clock pin, DDB7, PORTB7 and PINB7 will all read 0.• XTAL1/TOSC1 – Port B, Bit 6XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated RC Oscillator.
When used as a clock pin, the pin can not be used as an I/O pin.TOSC1: Timer Oscillator pin 1. Used only if internal calibrated RC Oscillator is selectedas chip clock source, and the asynchronous timer is enabled by the correct setting inASSR. When the AS2 bit in ASSR is set (one) to enable asynchronous clocking ofTimer/Counter2, pin PB6 is disconnected from the port, and becomes the input of the56ATmega8(L)2486O–AVR–10/04ATmega8(L)inverting Oscillator amplifier. In this mode, a crystal Oscillator is connected to this pin,and the pin can not be used as an I/O pin.If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0.• SCK – Port B, Bit 5SCK: Master Clock output, Slave Clock input pin for SPI channel.
When the SPI isenabled as a Slave, this pin is configured as an input regardless of the setting of DDB5.When the SPI is enabled as a Master, the data direction of this pin is controlled byDDB5. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit.• MISO – Port B, Bit 4MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI isenabled as a Master, this pin is configured as an input regardless of the setting ofDDB4. When the SPI is enabled as a Slave, the data direction of this pin is controlled byDDB4. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit.• MOSI/OC2 – Port B, Bit 3MOSI: SPI Master Data output, Slave Data input for SPI channel.
When the SPI isenabled as a Slave, this pin is configured as an input regardless of the setting of DDB3.When the SPI is enabled as a Master, the data direction of this pin is controlled byDDB3. When the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB3 bit.OC2, Output Compare Match Output: The PB3 pin can serve as an external output forthe Timer/Counter2 Compare Match. The PB3 pin has to be configured as an output(DDB3 set (one)) to serve this function. The OC2 pin is also the output pin for the PWMmode timer function.• SS/OC1B – Port B, Bit 2SS: Slave Select input.
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