ATmega8 (961722), страница 10
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;$c12HandlerrjmpSPM_RDY; Store Program Memory Ready$c13RESET: ldir16,high(RAMEND); Main program start$c14outSPH,r16$c15ldir16,low(RAMEND)$c16outSPL,r16$c17sei$c18<instr>; Set Stack Pointer to top of RAM; Enable interruptsxxxThe General Interrupt Control Register controls the placement of the Interrupt Vectortable.Bit76543210INT1INT0––––IVSELIVCERead/WriteR/WR/WRRRRR/WR/WInitial Value00000000GICR• Bit 1 – IVSEL: Interrupt Vector SelectWhen the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of theFlash memory.
When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the bootFlash section is determined by the BOOTSZ Fuses. Refer to the section “Boot LoaderSupport – Read-While-Write Self-Programming” on page 206 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followedto change the IVSEL bit:1. Write the Interrupt Vector Change Enable (IVCE) bit to one.2. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.Interrupts will automatically be disabled while this sequence is executed.
Interrupts aredisabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for fourcycles. The I-bit in the Status Register is unaffected by the automatic disabling.Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02is programmed, interrupts are disabled while executing from the Application section.
IfInterrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer tothe section “Boot Loader Support – Read-While-Write Self-Programming” on page 206for details on Boot Lock Bits.472486O–AVR–10/04• Bit 0 – IVCE: Interrupt Vector Change EnableThe IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE iscleared by hardware four cycles after it is written or when IVSEL is written.
Setting theIVCE bit will disable interrupts, as explained in the IVSEL description above. See CodeExample below.Assembly Code ExampleMove_interrupts:; Enable change of Interrupt Vectorsldi r16, (1<<IVCE)out GICR, r16; Move interrupts to boot Flash sectionldi r16, (1<<IVSEL)out GICR, r16retC Code Examplevoid Move_interrupts(void){/* Enable change of Interrupt Vectors */GICR = (1<<IVCE);/* Move interrupts to boot Flash section */GICR = (1<<IVSEL);}48ATmega8(L)2486O–AVR–10/04ATmega8(L)I/O PortsIntroductionAll AVR ports have true Read-Modify-Write functionality when used as general digitalI/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions.
Thesame applies when changing drive value (if configured as output) or enabling/disablingof pull-up resistors (if configured as input). Each output buffer has symmetrical drivecharacteristics with both high sink and source capability. The pin driver is strong enoughto drive LED displays directly. All port pins have individually selectable pull-up resistorswith a supply-voltage invariant resistance. All I/O pins have protection diodes to bothVCC and Ground as indicated in Figure 21.
Refer to “Electrical Characteristics” on page239 for a complete list of parameters.Figure 21. I/O Pin Equivalent SchematicRpuLogicPxnCpinSee Figure"General Digital I/O" forDetailsAll registers and bit references in this section are written in general form. A lower case“x” represents the numbering letter for the port, and a lower case “n” represents the bitnumber. However, when using the register or bit defines in a program, the precise formmust be used (i.e., PORTB3 for bit 3 in Port B, here documented generally as PORTxn).The physical I/O Registers and bit locations are listed in “Register Description for I/OPorts” on page 63.Three I/O memory address locations are allocated for each port, one each for the DataRegister – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx.
ThePort Input Pins I/O location is read only, while the Data Register and the Data DirectionRegister are read/write. In addition, the Pull-up Disable – PUD bit in SFIOR disables thepull-up function for all pins in all ports when set.Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” onpage 50. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is describedin “Alternate Port Functions” on page 54. Refer to the individual module sections for afull description of the alternate functions.Note that enabling the alternate function of some of the port pins does not affect the useof the other pins in the port as general digital I/O.492486O–AVR–10/04Ports as General DigitalI/OThe ports are bi-directional I/O ports with optional internal pull-ups.
Figure 22 shows afunctional description of one I/O port pin, here generically called Pxn.Figure 22. General Digital I/O(1)PUDQDDDxnQ CLRWDxRESETQPxnDPORTxnQ CLRWPxDATA BUSRDxRESETRRxSLEEPSYNCHRONIZERDQLQDRPxQPINxnQclk I/OPUD:SLEEP:clkI/O:Note:Configuring the PinPULLUP DISABLESLEEP CONTROLI/O CLOCKWDx:RDx:WPx:RRx:RPx:WRITE DDRxREAD DDRxWRITE PORTxREAD PORTx REGISTERREAD PORTx PIN1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,SLEEP, and PUD are common to all ports.Each port pin consists of 3 Register bits: DDxn, PORTxn, and PINxn. As shown in “Register Description for I/O Ports” on page 63, the DDxn bits are accessed at the DDRx I/Oaddress, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/Oaddress.The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is writtenlogic one, Pxn is configured as an output pin.
If DDxn is written logic zero, Pxn is configured as an input pin.If PORTxn is written logic one when the pin is configured as an input pin, the pull-upresistor is activated. To switch the pull-up resistor off, PORTxn has to be written logiczero or the pin has to be configured as an output pin.
The port pins are tri-stated when areset condition becomes active, even if no clocks are running.If PORTxn is written logic one when the pin is configured as an output pin, the port pin isdriven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).50ATmega8(L)2486O–AVR–10/04ATmega8(L)When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,PORTxn} = 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} =0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-upenabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up.
If this is not the case, the PUD bit inthe SFIOR Register can be set to disable all pull-ups in all ports.Switching between input with pull-up and output low generates the same problem. Theuser must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state({DDxn, PORTxn} = 0b11) as an intermediate step.Table 20 summarizes the control signals for the pin value.Table 20. Port Pin ConfigurationsReading the Pin ValueDDxnPORTxnPUD(in SFIOR)I/OPull-up00XInputNoTri-state (Hi-Z)010InputYesPxn will source current if externalpulled low.011InputNoTri-state (Hi-Z)10XOutputNoOutput Low (Sink)11XOutputNoOutput High (Source)CommentIndependent of the setting of Data Direction bit DDxn, the port pin can be read throughthe PINxn Register Bit.
As shown in Figure 22, the PINxn Register bit and the precedinglatch constitute a synchronizer. This is needed to avoid metastability if the physical pinchanges value near the edge of the internal clock, but it also introduces a delay. Figure23 shows a timing diagram of the synchronization when reading an externally appliedpin value. The maximum and minimum propagation delays are denoted t pd,max andtpd,min, respectively.Figure 23. Synchronization when Reading an Externally Applied Pin ValueSYSTEM CLKINSTRUCTIONSXXXXXXin r17, PINxSYNC LATCHPINxnr170x000xFFt pd, maxt pd, min512486O–AVR–10/04Consider the clock period starting shortly after the first falling edge of the system clock.The latch is closed when the clock is low, and goes transparent when the clock is high,as indicated by the shaded region of the “SYNC LATCH” signal.
The signal value islatched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a singlesignal transition on the pin will be delayed between ½ and 1-½ system clock perioddepending upon the time of assertion.When reading back a software assigned pin value, a nop instruction must be inserted asindicated in Figure 24. The out instruction sets the “SYNC LATCH” signal at the positiveedge of the clock.
In this case, the delay tpd through the synchronizer is 1 system clockperiod.Figure 24. Synchronization when Reading a Software Assigned Pin ValueSYSTEM CLKr16INSTRUCTIONS0xFFout PORTx, r16nopin r17, PINxSYNC LATCHPINxnr170x000xFFt pd52ATmega8(L)2486O–AVR–10/04ATmega8(L)The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, anddefine the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7.
Theresulting pin values are read back again, but as previously discussed, a nop instructionis included to be able to read back the value recently assigned to some of the pins.Assembly Code Example(1)...; Define pull-ups and set outputs high; Define directions for port pinsldir16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)ldir17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)outPORTB,r16outDDRB,r17; Insert nop for synchronizationnop; Read port pinsinr16,PINB...C Code Example(1)unsigned char i;.../* Define pull-ups and set outputs high *//* Define directions for port pins */PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);/* Insert nop for synchronization*/_NOP();/* Read port pins */i = PINB;...Note:Digital Input Enable and SleepModes1.
For the assembly program, two temporary registers are used to minimize the timefrom pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set,defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.As shown in Figure 22, the digital input signal can be clamped to ground at the input ofthe Schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU SleepController in Power-down mode, Power-save mode, and Standby mode to avoid highpower consumption if some input signals are left floating, or have an analog signal levelclose to VCC/2.SLEEP is overridden for port pins enabled as External Interrupt pins.
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