ATmega8 (961722), страница 12
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When the SPI is enabled as a Slave, this pin is configured as aninput regardless of the setting of DDB2. As a Slave, the SPI is activated when this pin isdriven low. When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB2. When the pin is forced by the SPI to be an input, the pull-up can still becontrolled by the PORTB2 bit.OC1B, Output Compare Match output: The PB2 pin can serve as an external output forthe Timer/Counter1 Compare Match B. The PB2 pin has to be configured as an output(DDB2 set (one)) to serve this function. The OC1B pin is also the output pin for the PWMmode timer function.• OC1A – Port B, Bit 1OC1A, Output Compare Match output: The PB1 pin can serve as an external output forthe Timer/Counter1 Compare Match A. The PB1 pin has to be configured as an output(DDB1 set (one)) to serve this function.
The OC1A pin is also the output pin for the PWMmode timer function.• ICP1 – Port B, Bit 0ICP1 – Input Capture Pin: The PB0 pin can act as an Input Capture Pin forTimer/Counter1.Table 23 and Table 24 relate the alternate functions of Port B to the overriding signalsshown in Figure 25 on page 54. SPI MSTR INPUT and SPI SLAVE OUTPUT constitutethe MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVEINPUT.572486O–AVR–10/04Table 23. Overriding Signals for Alternate Functions in PB7..PB4SignalNamePB7/XTAL2/TOSC2(1)(2)PB6/XTAL1/TOSC1(1)PB5/SCKPB4/MISOPUOEEXT • (INTRC +AS2)INTRC + AS2SPE • MSTRSPE • MSTRPUO00PORTB5 • PUDPORTB4 • PUDDDOEEXT • (INTRC +AS2)INTRC + AS2SPE • MSTRSPE • MSTRDDOV0000PVOE00SPE • MSTRSPE • MSTRPVOV00SCK OUTPUTSPI SLAVE OUTPUTDIEOEEXT • (INTRC +AS2)INTRC + AS200DIEOV0000DI––SCK INPUTSPI MSTR INPUTAIOOscillator OutputOscillator/ClockInput––Notes:1.
INTRC means that the internal RC Oscillator is selected (by the CKSEL Fuse).2. EXT means that the external RC Oscillator or an external clock is selected (by theCKSEL Fuse).Table 24. Overriding Signals for Alternate Functions in PB3..PB058SignalNamePB3/MOSI/OC2PB2/SS/OC1BPB1/OC1APB0/ICP1PUOESPE • MSTRSPE • MSTR00PUOPORTB3 • PUDPORTB2 • PUD00DDOESPE • MSTRSPE • MSTR00DDOV0000PVOESPE • MSTR +OC2 ENABLEOC1B ENABLEOC1A ENABLE0PVOVSPI MSTR OUTPUT + OC2OC1BOC1A0DIEOE0000DIEOV0000DISPI SLAVE INPUTSPI SS–ICP1 INPUTAIO––––ATmega8(L)2486O–AVR–10/04ATmega8(L)Alternate Functions of Port CThe Port C pins with alternate functions are shown in Table 25.Table 25.
Port C Pins Alternate FunctionsPort PinAlternate FunctionPC6RESET (Reset pin)PC5ADC5 (ADC Input Channel 5)SCL (Two-wire Serial Bus Clock Line)PC4ADC4 (ADC Input Channel 4)SDA (Two-wire Serial Bus Data Input/Output Line)PC3ADC3 (ADC Input Channel 3)PC2ADC2 (ADC Input Channel 2)PC1ADC1 (ADC Input Channel 1)PC0ADC0 (ADC Input Channel 0)The alternate pin configuration is as follows:• RESET – Port C, Bit 6RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as anormal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset asits reset sources.
When the RSTDISBL Fuse is unprogrammed, the reset circuitry isconnected to the pin, and the pin can not be used as an I/O pin.If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0.• SCL/ADC5 – Port C, Bit 5SCL, Two-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) toenable the Two-wire Serial Interface, pin PC5 is disconnected from the port andbecomes the Serial Clock I/O pin for the Two-wire Serial Interface.
In this mode, there isa spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and thepin is driven by an open drain driver with slew-rate limitation.PC5 can also be used as ADC input Channel 5. Note that ADC input channel 5 uses digital power.• SDA/ADC4 – Port C, Bit 4SDA, Two-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) toenable the Two-wire Serial Interface, pin PC4 is disconnected from the port andbecomes the Serial Data I/O pin for the Two-wire Serial Interface. In this mode, there isa spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and thepin is driven by an open drain driver with slew-rate limitation.PC4 can also be used as ADC input Channel 4.
Note that ADC input channel 4 uses digital power.• ADC3 – Port C, Bit 3PC3 can also be used as ADC input Channel 3. Note that ADC input channel 3 usesanalog power.• ADC2 – Port C, Bit 2PC2 can also be used as ADC input Channel 2. Note that ADC input channel 2 usesanalog power.• ADC1 – Port C, Bit 1592486O–AVR–10/04PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 usesanalog power.• ADC0 – Port C, Bit 0PC0 can also be used as ADC input Channel 0.
Note that ADC input channel 0 usesanalog power.Table 26 and Table 27 relate the alternate functions of Port C to the overriding signalsshown in Figure 25 on page 54.Table 26. Overriding Signals for Alternate Functions in PC6..PC4Signal NamePC6/RESETPC5/SCL/ADC5PC4/SDA/ADC4PUOERSTDISBLTWENTWENPUOV1PORTC5 • PUDPORTC4 • PUDDDOERSTDISBLTWENTWENDDOV0SCL_OUTSDA_OUTPVOE0TWENTWENPVOV000DIEOERSTDISBL00DIEOV000DI–––AIORESET INPUTADC5 INPUT / SCL INPUTADC4 INPUT / SDA INPUTTable 27. Overriding Signals for Alternate Functions in PC3..PC0(1)Signal NamePC3/ADC3PC2/ADC2PC1/ADC1PC0/ADC0PUOE0000PUOV0000DDOE0000DDOV0000PVOE0000PVOV0000DIEOE0000DIEOV0000DI––––AIOADC3 INPUTADC2 INPUTADC1 INPUTADC0 INPUTNote:601.
When enabled, the Two-wire Serial Interface enables slew-rate controls on the outputpins PC4 and PC5. This is not shown in the figure. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of theTWI module.ATmega8(L)2486O–AVR–10/04ATmega8(L)Alternate Functions of Port DThe Port D pins with alternate functions are shown in Table 28.Table 28. Port D Pins Alternate FunctionsPort PinAlternate FunctionPD7AIN1 (Analog Comparator Negative Input)PD6AIN0 (Analog Comparator Positive Input)PD5T1 (Timer/Counter 1 External Counter Input)PD4XCK (USART External Clock Input/Output)T0 (Timer/Counter 0 External Counter Input)PD3INT1 (External Interrupt 1 Input)PD2INT0 (External Interrupt 0 Input)PD1TXD (USART Output Pin)PD0RXD (USART Input Pin)The alternate pin configuration is as follows:• AIN1 – Port D, Bit 7AIN1, Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the functionof the Analog Comparator.• AIN0 – Port D, Bit 6AIN0, Analog Comparator Positive Input.
Configure the port pin as input with the internalpull-up switched off to avoid the digital port function from interfering with the function ofthe Analog Comparator.• T1 – Port D, Bit 5T1, Timer/Counter1 counter source.• XCK/T0 – Port D, Bit 4XCK, USART external clock.T0, Timer/Counter0 counter source.• INT1 – Port D, Bit 3INT1, External Interrupt source 1: The PD3 pin can serve as an external interruptsource.• INT0 – Port D, Bit 2INT0, External Interrupt source 0: The PD2 pin can serve as an external interruptsource.• TXD – Port D, Bit 1TXD, Transmit Data (Data output pin for the USART).
When the USART Transmitter isenabled, this pin is configured as an output regardless of the value of DDD1.• RXD – Port D, Bit 0RXD, Receive Data (Data input pin for the USART). When the USART Receiver isenabled this pin is configured as an input regardless of the value of DDD0. When theUSART forces this pin to be an input, the pull-up can still be controlled by thePORTD0 bit.612486O–AVR–10/04Table 29 and Table 30 relate the alternate functions of Port D to the overriding signalsshown in Figure 25 on page 54.Table 29.
Overriding Signals for Alternate Functions PD7..PD4Signal NamePD7/AIN1PD6/AIN0PD5/T1PD4/XCK/T0PUOE0000PUO0000OOE0000OO0000PVOE000UMSELPVO000XCK OUTPUTDIEOE0000DIEO0000DI––T1 INPUTXCK INPUT / T0 INPUTAIOAIN1 INPUTAIN0 INPUT––Table 30. Overriding Signals for Alternate Functions in PD3..PD062Signal NamePD3/INT1PD2/INT0PD1/TXDPD0/RXDPUOE00TXENRXENPUO000PORTD0 • PUDOOE00TXENRXENOO0010PVOE00TXEN0PVO00TXD0DIEOEINT1 ENABLEINT0 ENABLE00DIEO1100DIINT1 INPUTINT0 INPUT–RXDAIO––––ATmega8(L)2486O–AVR–10/04ATmega8(L)Register Description for I/O PortsThe Port B Data Register –PORTBThe Port B Data DirectionRegister – DDRBThe Port B Input Pins Address– PINBThe Port C Data Register –PORTCThe Port C Data DirectionRegister – DDRCThe Port C Input Pins Address– PINCThe Port D Data Register –PORTDThe Port D Data DirectionRegister – DDRDThe Port D Input Pins Address– PINDBit76543210PORTB7PORTB6PORTB5PORTB4PORTB3PORTB2PORTB1PORTB0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210DDB7DDB6DDB5DDB4DDB3DDB2DDB1DDB0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210PINB7PINB6PINB5PINB4PINB3PINB2PINB1PINB0Read/WriteRRRRRRRRInitial ValueN/AN/AN/AN/AN/AN/AN/AN/ABit76543210–PORTC6PORTC5PORTC4PORTC3PORTC2PORTC1PORTC0Read/WriteRR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210–DDC6DDC5DDC4DDC3DDC2DDC1DDC0Read/WriteRR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210–PINC6PINC5PINC4PINC3PINC2PINC1PINC0Read/WriteRRRRRRRRInitial Value0N/AN/AN/AN/AN/AN/AN/ABit76543210PORTD7PORTD6PORTD5PORTD4PORTD3PORTD2PORTD1PORTD0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210DDD7DDD6DDD5DDD4DDD3DDD2DDD1DDD0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000Bit76543210PIND7PIND6PIND5PIND4PIND3PIND2PIND1PIND0Read/WriteRRRRRRRRInitial ValueN/AN/AN/AN/AN/AN/AN/AN/APORTBDDRBPINBPORTCDDRCPINCPORTDDDRDPIND632486O–AVR–10/04External InterruptsThe external interrupts are triggered by the INT0, and INT1 pins.
Observe that, ifenabled, the interrupts will trigger even if the INT0..1 pins are configured as outputs.This feature provides a way of generating a software interrupt. The external interruptscan be triggered by a falling or rising edge or a low level. This is set up as indicated inthe specification for the MCU Control Register – MCUCR. When the external interrupt isenabled and is configured as level triggered, the interrupt will trigger as long as the pin isheld low.
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