ATmega8 (961722), страница 7
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A variation in frequency of morethan 2% from one clock cycle to the next can lead to unpredictable behavior. It isrequired to ensure that the MCU is kept in Reset during such changes in the clockfrequency.Timer/Counter Oscillator30For AVR microcontrollers with Timer/Counter Oscillator pins (TOSC1 and TOSC2), thecrystal is connected directly between the pins.
By programming the CKOPT Fuse, theuser can enable internal capacitors on XTAL1 and XTAL2, thereby removing the needfor external capacitors. The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock source to TOSC1 is not recommended.ATmega8(L)2486O–AVR–10/04ATmega8(L)Power Managementand Sleep ModesSleep modes enable the application to shut down unused modules in the MCU, therebysaving power.
The AVR provides various sleep modes allowing the user to tailor thepower consumption to the application’s requirements.To enter any of the five sleep modes, the SE bit in MCUCR must be written to logic oneand a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in theMCUCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down,Power-save, or Standby) will be activated by the SLEEP instruction. See Table 13 for asummary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCUwakes up. The MCU is then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and resumes execution from the instruction following SLEEP.The contents of the Register File and SRAM are unaltered when the device wakes upfrom sleep.
If a reset occurs during sleep mode, the MCU wakes up and executes fromthe Reset Vector.Note that the Extended Standby mode present in many other AVR MCUs has beenremoved in the ATmega8, as the TOSC and XTAL inputs share the same physical pins.Figure 10 on page 23 presents the different clock systems in the ATmega8, and theirdistribution. The figure is helpful in selecting an appropriate sleep mode.MCU Control Register –MCUCRThe MCU Control Register contains control bits for power management.Bit76543210SESM2SM1SM0ISC11ISC10ISC01ISC00Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000MCUCR• Bit 7 – SE: Sleep EnableThe SE bit must be written to logic one to make the MCU enter the sleep mode when theSLEEP instruction is executed.
To avoid the MCU entering the sleep mode unless it isthe programmer’s purpose, it is recommended to set the Sleep Enable (SE) bit justbefore the execution of the SLEEP instruction.• Bits 6..4 – SM2..0: Sleep Mode Select Bits 2, 1, and 0These bits select between the five available sleep modes as shown in Table 13.Table 13. Sleep Mode SelectNote:SM2SM1SM0Sleep Mode000Idle001ADC Noise Reduction010Power-down011Power-save100Reserved101Reserved110Standby(1)1.
Standby mode is only available with external crystals or resonators.312486O–AVR–10/04Idle ModeWhen the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enterIdle mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Twowire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continueoperating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the otherclocks to run.Idle mode enables the MCU to wake up from external triggered interrupts as well asinternal ones like the Timer Overflow and USART Transmit Complete interrupts.
Ifwake-up from the Analog Comparator interrupt is not required, the Analog Comparatorcan be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC isenabled, a conversion starts automatically when this mode is entered.ADC Noise ReductionModeWhen the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enterADC Noise Reduction mode, stopping the CPU but allowing the ADC, the externalinterrupts, the Two-wire Serial Interface address watch, Timer/Counter2 and theWatchdog to continue operating (if enabled). This sleep mode basically halts clk I/O,clkCPU, and clkFLASH, while allowing the other clocks to run.This improves the noise environment for the ADC, enabling higher resolution measurements.
If the ADC is enabled, a conversion starts automatically when this mode isentered. Apart form the ADC Conversion Complete interrupt, only an External Reset, aWatchdog Reset, a Brown-out Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter2 interrupt, an SPM/EEPROM ready interrupt, or an external levelinterrupt on INT0 or INT1, can wake up the MCU from ADC Noise Reduction mode.Power-down ModeWhen the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enterPower-down mode. In this mode, the External Oscillator is stopped, while the externalinterrupts, the Two-wire Serial Interface address watch, and the Watchdog continueoperating (if enabled).
Only an External Reset, a Watchdog Reset, a Brown-out Reset, aTwo-wire Serial Interface address match interrupt, or an external level interrupt on INT0or INT1, can wake up the MCU. This sleep mode basically halts all generated clocks,allowing operation of asynchronous modules only.Note that if a level triggered interrupt is used for wake-up from Power-down mode, thechanged level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 64 for details.When waking up from Power-down mode, there is a delay from the wake-up conditionoccurs until the wake-up becomes effective. This allows the clock to restart and becomestable after having been stopped.
The wake-up period is defined by the same CKSELFuses that define the Reset Time-out period, as described in “Clock Sources” on page24.Power-save ModeWhen the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enterPower-save mode. This mode is identical to Power-down, with one exception:If Timer/Counter2 is clocked asynchronously, i.e. the AS2 bit in ASSR is set,Timer/Counter2 will run during sleep. The device can wake up from either TimerOverflow or Output Compare event from Timer/Counter2 if the correspondingTimer/Counter2 interrupt enable bits are set in TIMSK, and the global interruptenable bit in SREG is set.If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recommended instead of Power-save mode because the contents of the registers in the32ATmega8(L)2486O–AVR–10/04ATmega8(L)asynchronous timer should be considered undefined after wake-up in Power-save modeif AS2 is 0.This sleep mode basically halts all clocks except clkASY, allowing operation only of asynchronous modules, including Timer/Counter 2 if clocked asynchronously.Standby ModeWhen the SM2..0 bits are 110 and an external crystal/resonator clock option is selected,the SLEEP instruction makes the MCU enter Standby mode.
This mode is identical toPower-down with the exception that the Oscillator is kept running. From Standby mode,the device wakes up in 6 clock cycles.Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep ModesActive Clock DomainsSleepModeOscillatorsclkCPU clkFLASH clkIO clkADC clkASYIdleXADC NoiseReductionWake-up SourcesTWISPM/Main ClockTimer Osc. INT1 Address Timer EEPROMOtherSource Enabled Enabled INT0 Match2Ready ADC I/OXXXX(2)XXXXXXXXX(2)X(3)XXXXX(3)XX(3)XX(3)XPowerDownPowerSaveX(2)Standby(1)Notes:X(2)XXX(2)1. External Crystal or resonator selected as clock source.2.
If AS2 bit in ASSR is set.3. Only level interrupt INT1 and INT0.Minimizing PowerConsumptionThere are several issues to consider when trying to minimize the power consumption inan AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’sfunctions are operating. All functions not needed should be disabled. In particular, thefollowing modules may need special consideration when trying to achieve the lowestpossible power consumption.Analog-to-Digital Converter(ADC)If enabled, the ADC will be enabled in all sleep modes.
To save power, the ADC shouldbe disabled before entering any sleep mode. When the ADC is turned off and on again,the next conversion will be an extended conversion. Refer to “Analog-to-Digital Converter” on page 193 for details on ADC operation.Analog ComparatorWhen entering Idle mode, the Analog Comparator should be disabled if not used.
Whenentering ADC Noise Reduction mode, the Analog Comparator should be disabled. In theother sleep modes, the Analog Comparator is automatically disabled. However, if theAnalog Comparator is set up to use the Internal Voltage Reference as input, the AnalogComparator should be disabled in all sleep modes.
Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” onpage 190 for details on how to configure the Analog Comparator.332486O–AVR–10/04Brown-out DetectorIf the Brown-out Detector is not needed in the application, this module should be turnedoff. If the Brown-out Detector is enabled by the BODEN Fuse, it will be enabled in allsleep modes, and hence, always consume power. In the deeper sleep modes, this willcontribute significantly to the total current consumption.
Refer to “Brown-out Detection”on page 38 for details on how to configure the Brown-out Detector.Internal Voltage ReferenceThe Internal Voltage Reference will be enabled when needed by the Brown-out Detector, the Analog Comparator or the ADC. If these modules are disabled as described inthe sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start upbefore the output is used.
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