ATmega8 (961722), страница 3
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Although not being physically implemented as SRAM locations, this memory organization provides greatflexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set toindex any register in the file.10ATmega8(L)2486O–AVR–10/04ATmega8(L)The X-register, Y-register andZ-registerThe registers R26..R31 have some added functions to their general purpose usage.These registers are 16-bit address pointers for indirect addressing of the Data Space.The three indirect address registers X, Y and Z are defined as described in Figure 4.Figure 4. The X-, Y- and Z-Registers15X-registerXHXL70R27 (0x1B)YHYL70R29 (0x1D)Z-register0R26 (0x1A)15Y-register07070R28 (0x1C)15ZH70ZL7R31 (0x1F)00R30 (0x1E)In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the Instruction SetReference for details).Stack PointerThe Stack is mainly used for storing temporary data, for storing local variables and forstoring return addresses after interrupts and subroutine calls.
The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growingfrom higher memory locations to lower memory locations. This implies that a StackPUSH command decreases the Stack Pointer.The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by theprogram before any subroutine calls are executed or interrupts are enabled. The StackPointer must be set to point above 0x60. The Stack Pointer is decremented by onewhen data is pushed onto the Stack with the PUSH instruction, and it is decremented bytwo when the return address is pushed onto the Stack with subroutine call or interrupt.The Stack Pointer is incremented by one when data is popped from the Stack with thePOP instruction, and it is incremented by two when address is popped from the Stackwith return from subroutine RET or return from interrupt RETI.The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space.
The number of bits actually used is implementation dependent. Note that the data space in someimplementations of the AVR architecture is so small that only SPL is needed. In thiscase, the SPH Register will not be present.BitRead/WriteInitial Value15141312111098SP15SP14SP13SP12SP11SP10SP9SP8SPHSP7SP6SP5SP4SP3SP2SP1SP0SPL76543210R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W0000000000000000112486O–AVR–10/04Instruction ExecutionTimingThis section describes the general access timing concepts for instruction execution. TheAVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clocksource for the chip.
No internal clock division is used.Figure 5 shows the parallel instruction fetches and instruction executions enabled by theHarvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results forfunctions per cost, functions per clocks, and functions per power-unit.Figure 5. The Parallel Instruction Fetches and Instruction ExecutionsT1T2T3T4clkCPU1st Instruction Fetch1st Instruction Execute2nd Instruction Fetch2nd Instruction Execute3rd Instruction Fetch3rd Instruction Execute4th Instruction FetchFigure 6 shows the internal timing concept for the Register File.
In a single clock cyclean ALU operation using two register operands is executed, and the result is stored backto the destination register.Figure 6. Single Cycle ALU OperationT1T2T3T4clkCPUTotal Execution TimeRegister Operands FetchALU Operation ExecuteResult Write BackReset and InterruptHandlingThe AVR provides several different interrupt sources. These interrupts and the separateReset Vector each have a separate Program Vector in the Program memory space.
Allinterrupts are assigned individual enable bits which must be written logic one togetherwith the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.Depending on the Program Counter value, interrupts may be automatically disabledwhen Boot Lock Bits BLB02 or BLB12 are programmed. This feature improves softwaresecurity. See the section “Memory Programming” on page 219 for details.The lowest addresses in the Program memory space are by default defined as theReset and Interrupt Vectors. The complete list of Vectors is shown in “Interrupts” onpage 44. The list also determines the priority levels of the different interrupts. The lowerthe address the higher is the priority level. RESET has the highest priority, and next isINT0 – the External Interrupt Request 0.
The Interrupt Vectors can be moved to the start12ATmega8(L)2486O–AVR–10/04ATmega8(L)of the boot Flash section by setting the Interrupt Vector Select (IVSEL) bit in the GeneralInterrupt Control Register (GICR). Refer to “Interrupts” on page 44 for more information.The Reset Vector can also be moved to the start of the boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write SelfProgramming” on page 206.When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interruptsare disabled.
The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit isautomatically set when a Return from Interrupt instruction – RETI – is executed.There are basically two types of interrupts. The first type is triggered by an event thatsets the Interrupt Flag.
For these interrupts, the Program Counter is vectored to theactual Interrupt Vector in order to execute the interrupt handling routine, and hardwareclears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing alogic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while thecorresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software.
Similarly, if one ormore interrupt conditions occur while the global interrupt enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the global interrupt enablebit is set, and will then be executed by order of priority.The second type of interrupts will trigger as long as the interrupt condition is present.These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine.
This must be handled bysoftware.When using the CLI instruction to disable interrupts, the interrupts will be immediatelydisabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used toavoid interrupts during the timed EEPROM write sequence.Assembly Code Examplein r16, SREGcli; store SREG value; disable interrupts during timed sequencesbi EECR, EEMWE; start EEPROM writesbi EECR, EEWEout SREG, r16; restore SREG value (I-bit)C Code Examplechar cSREG;cSREG = SREG; /* store SREG value *//* disable interrupts during timed sequence */_CLI();EECR |= (1<<EEMWE); /* start EEPROM write */EECR |= (1<<EEWE);SREG = cSREG; /* restore SREG value (I-bit) */132486O–AVR–10/04When using the SEI instruction to enable interrupts, the instruction following SEI will beexecuted before any pending interrupts, as shown in the following example.Assembly Code Examplesei; set global interrupt enablesleep; enter sleep, waiting for interrupt; note: will enter sleep before any pending; interrupt(s)C Code Example_SEI(); /* set global interrupt enable */_SLEEP(); /* enter sleep, waiting for interrupt *//* note: will enter sleep before any pending interrupt(s) */Interrupt Response TimeThe interrupt execution response for all the enabled AVR interrupts is four clock cyclesminimum.
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