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A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table15 on page 36. Shorter pulses are not guaranteed to generate a reset.52486O–AVR–10/04AVCCAVCC is the supply voltage pin for the A/D Converter, Port C (3..0), and ADC (7..6). Itshould be externally connected to VCC, even if the ADC is not used. If the ADC is used,it should be connected to VCC through a low-pass filter. Note that Port C (5..4) use digitalsupply voltage, VCC.AREFAREF is the analog reference pin for the A/D Converter.ADC7..6 (TQFP and MLFPackage Only)In the TQFP and MLF package, ADC7..6 serve as analog inputs to the A/D converter.These pins are powered from the analog supply and serve as 10-bit ADC channels.About CodeExamplesThis datasheet contains simple code examples that briefly show how to use variousparts of the device.
These code examples assume that the part specific header file isincluded before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Pleaseconfirm with the C compiler documentation for more details.6ATmega8(L)2486O–AVR–10/04ATmega8(L)AVR CPU CoreIntroductionThis section discusses the AVR core architecture in general. The main function of theCPU core is to ensure correct program execution.
The CPU must therefore be able toaccess memories, perform calculations, control peripherals, and handle interrupts.Architectural OverviewFigure 2. Block Diagram of the AVR MCU ArchitectureData Bus 8-bitFlashProgramMemoryProgramCounterStatusand Control32 x 8GeneralPurposeRegistrersControl LinesDirect AddressingInstructionDecoderIndirect AddressingInstructionRegisterInterruptUnitSPIUnitWatchdogTimerALUAnalogComparatori/O Module1DataSRAMi/O Module 2i/O Module nEEPROMI/O LinesIn order to maximize performance and parallelism, the AVR uses a Harvard architecture– with separate memories and buses for program and data. Instructions in the Programmemory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory.
This conceptenables instructions to be executed in every clock cycle. The Program memory is InSystem Reprogrammable Flash memory.The fast-access Register File contains 32 x 8-bit general purpose working registers witha single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)operation.
In a typical ALU operation, two operands are output from the Register File,the operation is executed, and the result is stored back in the Register File – in oneclock cycle.72486O–AVR–10/04Six of the 32 registers can be used as three 16-bit indirect address register pointers forData Space addressing – enabling efficient address calculations.
One of the theseaddress pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register,described later in this section.The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. Afteran arithmetic operation, the Status Register is updated to reflect information about theresult of the operation.The Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space.
Most AVR instructions have asingle 16-bit word format. Every Program memory address contains a 16- or 32-bitinstruction.Program Flash memory space is divided in two sections, the Boot program section andthe Application program section. Both sections have dedicated Lock Bits for write andread/write protection. The SPM instruction that writes into the Application Flash memorysection must reside in the Boot program section.During interrupts and subroutine calls, the return address Program Counter (PC) isstored on the Stack. The Stack is effectively allocated in the general data SRAM, andconsequently the Stack size is only limited by the total SRAM size and the usage of theSRAM.
All user programs must initialize the SP in the reset routine (before subroutinesor interrupts are executed). The Stack Pointer SP is read/write accessible in the I/Ospace. The data SRAM can easily be accessed through the five different addressingmodes supported in the AVR architecture.The memory spaces in the AVR architecture are all linear and regular memory maps.A flexible interrupt module has its control registers in the I/O space with an additionalglobal interrupt enable bit in the Status Register. All interrupts have a separate InterruptVector in the Interrupt Vector table. The interrupts have priority in accordance with theirInterrupt Vector position. The lower the Interrupt Vector address, the higher the priority.The I/O memory space contains 64 addresses for CPU peripheral functions as ControlRegisters, SPI, and other I/O functions.
The I/O Memory can be accessed directly, or asthe Data Space locations following those of the Register File, 0x20 - 0x5F.8ATmega8(L)2486O–AVR–10/04ATmega8(L)Arithmetic Logic Unit –ALUThe high-performance AVR ALU operates in direct connection with all the 32 generalpurpose working registers.
Within a single clock cycle, arithmetic operations betweengeneral purpose registers or between a register and an immediate are executed. TheALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multipliersupporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.Status RegisterThe Status Register contains information about the result of the most recently executedarithmetic instruction. This information can be used for altering program flow in order toperform conditional operations.
Note that the Status Register is updated after all ALUoperations, as specified in the Instruction Set Reference. This will in many casesremove the need for using the dedicated compare instructions, resulting in faster andmore compact code.The Status Register is not automatically stored when entering an interrupt routine andrestored when returning from an interrupt. This must be handled by software.The AVR Status Register – SREG – is defined as:Bit76543210ITHSVNZCRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000SREG• Bit 7 – I: Global Interrupt EnableThe Global Interrupt Enable bit must be set for the interrupts to be enabled.
The individual interrupt enable control is then performed in separate control registers. If the GlobalInterrupt Enable Register is cleared, none of the interrupts are enabled independent ofthe individual interrupt enable settings. The I-bit is cleared by hardware after an interrupthas occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit can also be set and cleared by the application with the SEI and CLI instructions, asdescribed in the Instruction Set Reference.• Bit 6 – T: Bit Copy StorageThe Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source ordestination for the operated bit.
A bit from a register in the Register File can be copiedinto T by the BST instruction, and a bit in T can be copied into a bit in a register in theRegister File by the BLD instruction.• Bit 5 – H: Half Carry FlagThe Half Carry Flag H indicates a Half Carry in some arithmetic operations.
Half Carry isuseful in BCD arithmetic. See the “Instruction Set Description” for detailed information.• Bit 4 – S: Sign Bit, S = N⊕VThe S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.• Bit 3 – V: Two’s Complement Overflow FlagThe Two’s Complement Overflow Flag V supports two’s complement arithmetics. Seethe “Instruction Set Description” for detailed information.• Bit 2 – N: Negative FlagThe Negative Flag N indicates a negative result in an arithmetic or logic operation. Seethe “Instruction Set Description” for detailed information.• Bit 1 – Z: Zero Flag92486O–AVR–10/04The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the“Instruction Set Description” for detailed information.• Bit 0 – C: Carry FlagThe Carry Flag C indicates a Carry in an arithmetic or logic operation.
See the “Instruction Set Description” for detailed information.General PurposeRegister FileThe Register File is optimized for the AVR Enhanced RISC instruction set. In order toachieve the required performance and flexibility, the following input/output schemes aresupported by the Register File:•One 8-bit output operand and one 8-bit result input.•Two 8-bit output operands and one 8-bit result input.•Two 8-bit output operands and one 16-bit result input.•One 16-bit output operand and one 16-bit result input.Figure 3 shows the structure of the 32 general purpose working registers in the CPU.Figure 3.
AVR CPU General Purpose Working Registers70Addr.R00x00R10x01R20x02…R130x0DGeneralR140x0EPurposeR150x0FWorkingR160x10RegistersR170x11…R260x1AX-register Low ByteR270x1BX-register High ByteR280x1CY-register Low ByteR290x1DY-register High ByteR300x1EZ-register Low ByteR310x1FZ-register High ByteMost of the instructions operating on the Register File have direct access to all registers,and most of them are single cycle instructions.As shown in Figure 3, each register is also assigned a Data memory address, mappingthem directly into the first 32 locations of the user Data Space.
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