ATmega8 (961722), страница 4
Текст из файла (страница 4)
After four clock cycles, the Program Vector address for the actual interrupthandling routine is executed. During this 4-clock cycle period, the Program Counter ispushed onto the Stack. The Vector is normally a jump to the interrupt routine, and thisjump takes three clock cycles. If an interrupt occurs during execution of a multi-cycleinstruction, this instruction is completed before the interrupt is served. If an interruptoccurs when the MCU is in sleep mode, the interrupt execution response time isincreased by four clock cycles. This increase comes in addition to the start-up time fromthe selected sleep mode.A return from an interrupt handling routine takes four clock cycles. During these fourclock cycles, the Program Counter (2 bytes) is popped back from the Stack, the StackPointer is incremented by 2, and the I-bit in SREG is set.14ATmega8(L)2486O–AVR–10/04ATmega8(L)AVR ATmega8MemoriesThis section describes the different memories in the ATmega8.
The AVR architecturehas two main memory spaces, the Data memory and the Program Memory space. Inaddition, the ATmega8 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.In-SystemReprogrammable FlashProgram MemoryThe ATmega8 contains 8K bytes On-chip In-System Reprogrammable Flash memoryfor program storage. Since all AVR instructions are 16- or 32-bits wide, the Flash isorganized as 4K x 16 bits.
For software security, the Flash Program memory space isdivided into two sections, Boot Program section and Application Program section.The Flash memory has an endurance of at least 10,000 write/erase cycles. TheATmega8 Program Counter (PC) is 12 bits wide, thus addressing the 4K Program memory locations. The operation of Boot Program section and associated Boot Lock Bits forsoftware protection are described in detail in “Boot Loader Support – Read-While-WriteSelf-Programming” on page 206.
“Memory Programming” on page 219 contains adetailed description on Flash Programming in SPI- or Parallel Programming mode.Constant tables can be allocated within the entire Program memory address space (seethe LPM – Load Program memory instruction description).Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 12.Figure 7.
Program Memory Map$000Application Flash SectionBoot Flash Section$FFF152486O–AVR–10/04SRAM Data MemoryFigure 8 shows how the ATmega8 SRAM Memory is organized.The lower 1120 Data memory locations address the Register File, the I/O Memory, andthe internal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next 1024 locations address the internal data SRAM.The five different addressing modes for the Data memory cover: Direct, Indirect withDisplacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. Inthe Register File, registers R26 to R31 feature the indirect addressing pointer registers.The direct addressing reaches the entire data space.The Indirect with Displacement mode reaches 63 address locations from the baseaddress given by the Y- or Z-register.When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y and Z are decremented or incremented.The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data SRAM in the ATmega8 are all accessible through all these addressing modes.The Register File is described in “General Purpose Register File” on page 10.Figure 8.
Data Memory MapRegister FileData Address SpaceR0R1R2...$0000$0001$0002...R29R30R31I/O Registers$00$01$02...$001D$001E$001F$3D$3E$3F$005D$005E$005FInternal SRAM$0060$0061...$0020$0021$0022...$045E$045F16ATmega8(L)2486O–AVR–10/04ATmega8(L)Data Memory AccessTimesThis section describes the general access timing concepts for internal memory access.The internal data SRAM access is performed in two clkCPU cycles as described in Figure9.Figure 9.
On-chip Data SRAM Access CyclesT1T2T3clkCPUAddressCompute AddressAddress ValidWriteDataWRReadDataRDMemory Vccess InstructionEEPROM Data MemoryNext InstructionThe ATmega8 contains 512 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has anendurance of at least 100,000 write/erase cycles.
The access between the EEPROMand the CPU is described bellow, specifying the EEPROM Address Registers, theEEPROM Data Register, and the EEPROM Control Register.“Memory Programming” on page 219 contains a detailed description on EEPROM Programming in SPI- or Parallel Programming mode.EEPROM Read/Write AccessThe EEPROM Access Registers are accessible in the I/O space.The write access time for the EEPROM is given in Table 1 on page 19.
A self-timingfunction, however, lets the user software detect when the next byte can be written. If theuser code contains instructions that write the EEPROM, some precautions must betaken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on Powerup/down. This causes the device for some period of time to run at a voltage lower thanspecified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 21.
for details on how to avoid problems in these situations.In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.When the EEPROM is read, the CPU is halted for four clock cycles before the nextinstruction is executed. When the EEPROM is written, the CPU is halted for two clockcycles before the next instruction is executed.172486O–AVR–10/04The EEPROM AddressRegister – EEARH and EEARLBitRead/WriteInitial Value15141312111098–––––––EEAR8EEARHEEAR7EEAR6EEAR5EEAR4EEAR3EEAR2EEAR1EEAR0EEARL76543210RRRRRRRR/WR/WR/WR/WR/WR/WR/WR/WR/W0000000XXXXXXXXX• Bits 15..9 – Res: Reserved BitsThese bits are reserved bits in the ATmega8 and will always read as zero.• Bits 8..0 – EEAR8..0: EEPROM AddressThe EEPROM Address Registers – EEARH and EEARL – specify the EEPROMaddress in the 512 bytes EEPROM space.
The EEPROM data bytes are addressed linearly between 0 and 511. The initial value of EEAR is undefined. A proper value must bewritten before the EEPROM may be accessed.The EEPROM Data Register –EEDRBit7654321MSB0LSBRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000EEDR• Bits 7..0 – EEDR7..0: EEPROM DataFor the EEPROM write operation, the EEDR Register contains the data to be written tothe EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given byEEAR.The EEPROM Control Register– EECRBit76543210––––EERIEEEMWEEEWEEERERead/WriteRRRRR/WR/WR/WR/WInitial Value000000X0EECR• Bits 7..4 – Res: Reserved BitsThese bits are reserved bits in the ATmega8 and will always read as zero.• Bit 3 – EERIE: EEPROM Ready Interrupt EnableWriting EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set.Writing EERIE to zero disables the interrupt.
The EEPROM Ready interrupt generates aconstant interrupt when EEWE is cleared.• Bit 2 – EEMWE: EEPROM Master Write EnableThe EEMWE bit determines whether setting EEWE to one causes the EEPROM to bewritten. When EEMWE is set, setting EEWE within four clock cycles will write data to theEEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect.When EEMWE has been written to one by software, hardware clears the bit to zero afterfour clock cycles. See the description of the EEWE bit for an EEPROM write procedure.• Bit 1 – EEWE: EEPROM Write EnableThe EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. Whenaddress and data are correctly set up, the EEWE bit must be written to one to write the18ATmega8(L)2486O–AVR–10/04ATmega8(L)value into the EEPROM. The EEMWE bit must be written to one before a logical one iswritten to EEWE, otherwise no EEPROM write takes place.
The following procedureshould be followed when writing the EEPROM (the order of steps 3 and 4 is notessential):1. Wait until EEWE becomes zero.2. Wait until SPMEN in SPMCR becomes zero.3. Write new EEPROM address to EEAR (optional).4. Write new EEPROM data to EEDR (optional).5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.The EEPROM can not be programmed during a CPU write to the Flash memory. Thesoftware must check that the Flash programming is completed before initiating a newEEPROM write. Step 2 is only relevant if the software contains a boot loader allowingthe CPU to program the Flash.
If the Flash is never being updated by the CPU, step 2can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming” onpage 206 for details about boot programming.Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since theEEPROM Master Write Enable will time-out. If an interrupt routine accessing theEEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will bemodified, causing the interrupted EEPROM access to fail. It is recommended to havethe Global Interrupt Flag cleared during all the steps to avoid these problems.When the write access time has elapsed, the EEWE bit is cleared by hardware.
Theuser software can poll this bit and wait for a zero before writing the next byte. WhenEEWE has been set, the CPU is halted for two cycles before the next instruction isexecuted.• Bit 0 – EERE: EEPROM Read EnableThe EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When thecorrect address is set up in the EEAR Register, the EERE bit must be written to a logicone to trigger the EEPROM read.
The EEPROM read access takes one instruction, andthe requested data is available immediately. When the EEPROM is read, the CPU ishalted for four cycles before the next instruction is executed.The user should poll the EEWE bit before starting the read operation. If a write operationis in progress, it is neither possible to read the EEPROM, nor to change the EEARRegister.The calibrated Oscillator is used to time the EEPROM accesses. Table 1 lists the typicalprogramming time for EEPROM access from the CPU.Table 1. EEPROM Programming TimeSymbolEEPROM Write (from CPU)Note:Number of Calibrated RCOscillator Cycles(1)Typ Programming Time84488.5 ms1. Uses 1 MHz clock, independent of CKSEL Fuse settings.192486O–AVR–10/04The following code examples show one assembly and one C function for writing to theEEPROM.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
