ATmega8 (961722), страница 5
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The examples assume that interrupts are controlled (for example by disabling interrupts globally) so that no interrupts will occur during execution of thesefunctions. The examples also assume that no Flash boot loader is present in the software. If such code is present, the EEPROM write function must also wait for anyongoing SPM command to finish.Assembly Code ExampleEEPROM_write:; Wait for completion of previous writesbic EECR,EEWErjmp EEPROM_write; Set up address (r18:r17) in address registerout EEARH, r18out EEARL, r17; Write data (r16) to data registerout EEDR,r16; Write logical one to EEMWEsbi EECR,EEMWE; Start eeprom write by setting EEWEsbi EECR,EEWEretC Code Examplevoid EEPROM_write(unsigned int uiAddress, unsigned char ucData){/* Wait for completion of previous write */while(EECR & (1<<EEWE));/* Set up address and data registers */EEAR = uiAddress;EEDR = ucData;/* Write logical one to EEMWE */EECR |= (1<<EEMWE);/* Start eeprom write by setting EEWE */EECR |= (1<<EEWE);}20ATmega8(L)2486O–AVR–10/04ATmega8(L)The next code examples show assembly and C functions for reading the EEPROM.
Theexamples assume that interrupts are controlled so that no interrupts will occur duringexecution of these functions.Assembly Code ExampleEEPROM_read:; Wait for completion of previous writesbic EECR,EEWErjmp EEPROM_read; Set up address (r18:r17) in address registerout EEARH, r18out EEARL, r17; Start eeprom read by writing EEREsbi EECR,EERE; Read data from data registerinr16,EEDRretC Code Exampleunsigned char EEPROM_read(unsigned int uiAddress){/* Wait for completion of previous write */while(EECR & (1<<EEWE));/* Set up address register */EEAR = uiAddress;/* Start eeprom read by writing EERE */EECR |= (1<<EERE);/* Return data from data register */return EEDR;}EEPROM Write during Powerdown Sleep ModeWhen entering Power-down sleep mode while an EEPROM write operation is active, theEEPROM write operation will continue, and will complete before the Write Access timehas passed. However, when the write operation is completed, the Oscillator continuesrunning, and as a consequence, the device does not enter Power-down entirely.
It istherefore recommended to verify that the EEPROM write operation is completed beforeentering Power-down.Preventing EEPROMCorruptionDuring periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are thesame as for board level systems using EEPROM, and the same design solutions shouldbe applied.An EEPROM data corruption can be caused by two situations when the voltage is toolow.
First, a regular write sequence to the EEPROM requires a minimum voltage tooperate correctly. Second, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.EEPROM data corruption can easily be avoided by following this designrecommendation:212486O–AVR–10/04Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD). If thedetection level of the internal BOD does not match the needed detection level, anexternal low VCC Reset Protection circuit can be used. If a reset occurs while a writeoperation is in progress, the write operation will be completed provided that thepower supply voltage is sufficient.I/O MemoryThe I/O space definition of the ATmega8 is shown in “” on page 284.All ATmega8 I/Os and peripherals are placed in the I/O space.
The I/O locations areaccessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers,the value of single bits can be checked by using the SBIS and SBIC instructions.
Referto the instruction set section for more details. When using the I/O specific commands INand OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registersas data space using LD and ST instructions, 0x20 must be added to these addresses.For compatibility with future devices, reserved bits should be written to zero if accessed.Reserved I/O memory addresses should never be written.Some of the Status Flags are cleared by writing a logical one to them.
Note that the CBIand SBI instructions will operate on all bits in the I/O Register, writing a one back intoany flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers 0x00 to 0x1F only.The I/O and Peripherals Control Registers are explained in later sections.22ATmega8(L)2486O–AVR–10/04ATmega8(L)System Clock andClock OptionsClock Systems and theirDistributionFigure 10 presents the principal clock systems in the AVR and their distribution.
All ofthe clocks need not be active at a given time. In order to reduce power consumption, theclocks to modules not being used can be halted by using different sleep modes, asdescribed in “Power Management and Sleep Modes” on page 31. The clock systemsare detailed Figure 10.Figure 10.
Clock DistributionAsynchronousTimer/CounterGeneral I/OModulesADCCPU CoreRAMFlash andEEPROMclkADCclkI/OAVR ClockControl UnitclkASYclkCPUclkFLASHReset LogicSource ClockWatchdog ClockClockMultiplexerTimer/CounterOscillatorExternal RCOscillatorExternal ClockWatchdog TimerWatchdogOscillatorCrystalOscillatorLow-FrequencyCrystal OscillatorCalibrated RCOscillatorCPU Clock – clkCPUThe CPU clock is routed to parts of the system concerned with operation of the AVRcore. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory holding the Stack Pointer.
Halting the CPU clock inhibits thecore from performing general operations and calculations.I/O Clock – clkI/OThe I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, andUSART. The I/O clock is also used by the External Interrupt module, but note that someexternal interrupts are detected by asynchronous logic, allowing such interrupts to bedetected even if the I/O clock is halted.
Also note that address recognition in the TWImodule is carried out asynchronously when clkI/O is halted, enabling TWI address reception in all sleep modes.Flash Clock – clkFLASHThe Flash clock controls operation of the Flash interface. The Flash clock is usuallyactive simultaneously with the CPU clock.232486O–AVR–10/04Asynchronous Timer Clock –clkASYThe Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clockeddirectly from an external 32 kHz clock crystal. The dedicated clock domain allows usingthis Timer/Counter as a real-time counter even when the device is in sleep mode. TheAsynchronous Timer/Counter uses the same XTAL pins as the CPU main clock butrequires a CPU main clock frequency of more than four times the Oscillator frequency.Thus, asynchronous operation is only available while the chip is clocked on the InternalOscillator.ADC Clock – clkADCThe ADC is provided with a dedicated clock domain.
This allows halting the CPU andI/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.Clock SourcesThe device has the following clock source options, selectable by Flash Fuse Bits asshown below. The clock from the selected source is input to the AVR clock generator,and routed to the appropriate modules.Table 2. Device Clocking Options Select(1)Device Clocking OptionCKSEL3..0External Crystal/Ceramic Resonator1111 - 1010External Low-frequency Crystal1001External RC Oscillator1000 - 0101Calibrated Internal RC Oscillator0100 - 0001External ClockNote:00001.
For all fuses “1” means unprogrammed while “0” means programmed.The various choices for each clocking option is given in the following sections. When theCPU wakes up from Power-down or Power-save, the selected clock source is used totime the start-up, ensuring stable Oscillator operation before instruction execution starts.When the CPU starts from reset, there is as an additional delay allowing the power toreach a stable level before commencing normal operation.
The Watchdog Oscillator isused for timing this real-time part of the start-up time. The number of WDT Oscillatorcycles used for each time-out is shown in Table 3. The frequency of the Watchdog Oscillator is voltage dependent as shown in “ATmega8 Typical Characteristics”. The device isshipped with CKSEL = “0001” and SUT = “10” (1 MHz Internal RC Oscillator, slowly rising power).Table 3. Number of Watchdog Oscillator Cycles24Typical Time-out (VCC = 5.0V)Typical Time-out (VCC = 3.0V)Number of Cycles4.1 ms4.3 ms4K (4,096)65 ms69 ms64K (65,536)ATmega8(L)2486O–AVR–10/04ATmega8(L)Crystal OscillatorXTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which canbe configured for use as an On-chip Oscillator, as shown in Figure 11.
Either a quartzcrystal or a ceramic resonator may be used. The CKOPT Fuse selects between two different Oscillator amplifier modes. When CKOPT is programmed, the Oscillator outputwill oscillate a full rail-to-rail swing on the output. This mode is suitable when operatingin a very noisy environment or when the output from XTAL2 drives a second clockbuffer.
This mode has a wide frequency range. When CKOPT is unprogrammed, theOscillator has a smaller output swing. This reduces power consumption considerably.This mode has a limited frequency range and it cannot be used to drive other clockbuffers.For resonators, the maximum frequency is 8 MHz with CKOPT unprogrammed and16 MHz with CKOPT programmed. C1 and C2 should always be equal for both crystalsand resonators.
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