ATmega8 (961722), страница 23
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The PWM waveform is generated by setting (or clearing) the OC2Register at the Compare Match between OCR2 and TCNT2, and clearing (or setting)the OC2 Register at the timer clock cycle the counter is cleared (changes from MAX toBOTTOM).110ATmega8(L)2486O–AVR–10/04ATmega8(L)The PWM frequency for the output can be calculated by the following equation:f clk_I/Of OCnPWM = ----------------N ⋅ 256The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).The extreme values for the OCR2 Register represent special cases when generating aPWM waveform output in the fast PWM mode. If the OCR2 is set equal to BOTTOM, theoutput will be a narrow spike for each MAX+1 timer clock cycle.
Setting the OCR2 equalto MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM21:0 bits.)A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achievedby setting OC2 to toggle its logical level on each Compare Match (COM21:0 = 1). Thewaveform generated will have a maximum frequency of foc2 = fclk_I/O/2 when OCR2 is setto zero. This feature is similar to the OC2 toggle in CTC mode, except the double bufferfeature of the Output Compare unit is enabled in the fast PWM mode.Phase Correct PWM ModeThe phase correct PWM mode (WGM21:0 = 1) provides a high resolution phase correctPWM waveform generation option.
The phase correct PWM mode is based on a dualslope operation. The counter counts repeatedly from BOTTOM to MAX and then fromMAX to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC2)is cleared on the Compare Match between TCNT2 and OCR2 while upcounting, and seton the Compare Match while downcounting. In inverting Output Compare mode, theoperation is inverted. The dual-slope operation has lower maximum operation frequencythan single slope operation. However, due to the symmetric feature of the dual-slopePWM modes, these modes are preferred for motor control applications.The PWM resolution for the phase correct PWM mode is fixed to eight bits.
In phasecorrect PWM mode the counter is incremented until the counter value matches MAX.When the counter reaches MAX, it changes the count direction. The TCNT2 value willbe equal to MAX for one timer clock cycle. The timing diagram for the phase correctPWM mode is shown on Figure 51. The TCNT2 value is in the timing diagram shown asa histogram for illustrating the dual-slope operation. The diagram includes non-invertedand inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2 and TCNT2.1112486O–AVR–10/04Figure 51.
Phase Correct PWM Mode, Timing DiagramOCn Interrupt Flag SetOCRn UpdateTOVn Interrupt Flag SetTCNTnOCn(COMn1:0 = 2)OCn(COMn1:0 = 3)Period123The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counterreaches the BOTTOM value.In phase correct PWM mode, the compare unit allows generation of PWM waveforms onthe OC2 pin.
Setting the COM21:0 bits to 2 will produce a non-inverted PWM. Aninverted PWM output can be generated by setting the COM21:0 to 3 (see Table 45 onpage 116). The actual OC2 value will only be visible on the port pin if the data directionfor the port pin is set as output. The PWM waveform is generated by clearing (or setting)the OC2 Register at the Compare Match between OCR2 and TCNT2 when the counterincrements, and setting (or clearing) the OC2 Register at Compare Match betweenOCR2 and TCNT2 when the counter decrements.
The PWM frequency for the outputwhen using phase correct PWM can be calculated by the following equation:f clk_I/Of OCnPCPWM = ----------------N ⋅ 510The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).The extreme values for the OCR2 Register represent special cases when generating aPWM waveform output in the phase correct PWM mode. If the OCR2 is set equal toBOTTOM, the output will be continuously low and if set equal to MAX the output will becontinuously high for non-inverted PWM mode. For inverted PWM the output will havethe opposite logic values.At the very start of period 2 in Figure 51 OCn has a transition from high to low eventhough there is no Compare Match.
The point of this transition is to guarantee symmetryaround BOTTOM. There are two cases that give a transition without Compare Match:•112OCR2A changes its value from MAX, like in Figure 51. When the OCR2A value isMAX the OCn pin value is the same as the result of a down-counting CompareMatch. To ensure symmetry around BOTTOM the OCn value at MAX mustcorrespond to the result of an up-counting Compare Match.ATmega8(L)2486O–AVR–10/04ATmega8(L)•Timer/Counter TimingDiagramsThe timer starts counting from a value higher than the one in OCR2A, and for thatreason misses the Compare Match and hence the OCn change that would havehappened on the way up.The following figures show the Timer/Counter in Synchronous mode, and the timer clock(clkT2) is therefore shown as a clock enable signal. In Asynchronous mode, clkI/O shouldbe replaced by the Timer/Counter Oscillator clock. The figures include information onwhen Interrupt Flags are set.
Figure 52 contains timing data for basic Timer/Counteroperation. The figure shows the count sequence close to the MAX value in all modesother than phase correct PWM mode.Figure 52. Timer/Counter Timing Diagram, no PrescalingclkI/OclkTn(clkI/O /1)TCNTnMAX - 1MAXBOTTOMBOTTOM + 1TOVnFigure 53 shows the same timing data, but with the prescaler enabled.Figure 53.
Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)clkI/OclkTn(clkI/O /8)TCNTnMAX - 1MAXBOTTOMBOTTOM + 1TOVnFigure 54 shows the setting of OCF2 in all modes except CTC mode.1132486O–AVR–10/04Figure 54. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (fclk_I/O/8)clkI/OclkTn(clkI/O /8)TCNTnOCRn - 1OCRnOCRnOCRn + 1OCRn + 2OCRn ValueOCFnFigure 55 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode.Figure 55. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, withPrescaler (fclk_I/O/8)clkI/OclkTn(clkI/O /8)TCNTn(CTC)OCRnTOP - 1TOPBOTTOMBOTTOM + 1TOPOCFn114ATmega8(L)2486O–AVR–10/04ATmega8(L)8-bit Timer/CounterRegister DescriptionTimer/Counter ControlRegister – TCCR2Bit76543210FOC2WGM20COM21COM20WGM21CS22CS21CS20Read/WriteWR/WR/WR/WR/WR/WR/WR/WInitial Value00000000TCCR2• Bit 7 – FOC2: Force Output CompareThe FOC2 bit is only active when the WGM bits specify a non-PWM mode.
However, forensuring compatibility with future devices, this bit must be set to zero when TCCR2 iswritten when operating in PWM mode. When writing a logical one to the FOC2 bit, animmediate Compare Match is forced on the waveform generation unit. The OC2 outputis changed according to its COM21:0 bits setting. Note that the FOC2 bit is implementedas a strobe. Therefore it is the value present in the COM21:0 bits that determines theeffect of the forced compare.A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC modeusing OCR2 as TOP.The FOC2 bit is always read as zero.• Bit 6,3 – WGM21:0: Waveform Generation ModeThese bits control the counting sequence of the counter, the source for the maximum(TOP) counter value, and what type of waveform generation to be used.
Modes of operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on CompareMatch (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See Table42 and “Modes of Operation” on page 108.Table 42. Waveform Generation Mode Bit DescriptionModeWGM21(CTC2)WGM20(PWM2)Timer/Counter Modeof Operation(1)TOPUpdate ofOCR2TOV2 FlagSet000Normal0xFFImmediateMAX101PWM, Phase Correct0xFFTOPBOTTOM210CTCOCR2ImmediateMAX311Fast PWM0xFFTOPMAXNote:1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions. However, the functionality and location of these bits are compatible withprevious versions of the timer.• Bit 5:4 – COM21:0: Compare Match Output ModeThese bits control the Output Compare Pin (OC2) behavior. If one or both of theCOM21:0 bits are set, the OC2 output overrides the normal port functionality of the I/Opin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set in order to enable the output driver.When OC2 is connected to the pin, the function of the COM21:0 bits depends on theWGM21:0 bit setting. Table 43 shows the COM21:0 bit functionality when the WGM21:0bits are set to a normal or CTC mode (non-PWM).1152486O–AVR–10/04Table 43. Compare Output Mode, Non-PWM ModeCOM21COM20Description00Normal port operation, OC2 disconnected.01Toggle OC2 on Compare Match10Clear OC2 on Compare Match11Set OC2 on Compare MatchTable 44 shows the COM21:0 bit functionality when the WGM21:0 bits are set to fastPWM mode.Table 44.
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