ATmega8 (961722), страница 25
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In PWM mode, this bit is set whenTimer/Counter2 changes counting direction at 0x00.120ATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 56. Prescaler for Timer/Counter2clkT2SPSR2clkT2S/1024clkT2S/256clkT2S/8AS2clkT2S/12810-BIT T/C PRESCALERClearTOSC1clkT2S/64clkI/OclkT2S/32Timer/Counter Prescaler0CS20CS21CS22TIMER/COUNTER2 CLOCK SOURCEclkT2The clock source for Timer/Counter2 is named clkT2S.
clkT2S is by default connected tothe main system I/O clock clkI/O. By setting the AS2 bit in ASSR, Timer/Counter2 isasynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as aReal Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnectedfrom Port B. A crystal can then be connected between the TOSC1 and TOSC2 pins toserve as an independent clock source for Timer/Counter2. The Oscillator is optimizedfor use with a 32.768 kHz crystal. Applying an external clock source to TOSC1 is notrecommended.For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64,clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may beselected. Setting the PSR2 bit in SFIOR resets the prescaler.
This allows the user tooperate with a predictable prescaler.Special Function IO Register –SFIORBit76543210––––ACMEPUDPSR2PSR10Read/WriteRRRRR/WR/WR/WR/WInitial Value00000000SFIOR• Bit 1 – PSR2: Prescaler Reset Timer/Counter2When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will becleared by hardware after the operation is performed.
Writing a zero to this bit will haveno effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internalCPU clock. If this bit is written when Timer/Counter2 is operating in Asynchronousmode, the bit will remain one until the prescaler has been reset.1212486O–AVR–10/04Serial PeripheralInterface – SPIThe Serial Peripheral Interface (SPI) allows high-speed synchronous data transferbetween the ATmega8 and peripheral devices or between several AVR devices. TheATmega8 SPI includes the following features:• Full-duplex, Three-wire Synchronous Data Transfer• Master or Slave Operation• LSB First or MSB First Data Transfer• Seven Programmable Bit Rates• End of Transmission Interrupt Flag• Write Collision Flag Protection• Wake-up from Idle Mode• Double Speed (CK/2) Master SPI ModeFigure 57.
SPI Block Diagram(1)SPI2XSPI2XDIVIDER/2/4/8/16/32/64/128Note:1. Refer to “Pin Configurations” on page 2, and Table 22 on page 56 for SPI pinplacement.The interconnection between Master and Slave CPUs with SPI is shown in Figure 58.The system consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of thedesired Slave. Master and Slave prepare the data to be sent in their respective ShiftRegisters, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In,MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. Aftereach data packet, the Master will synchronize the Slave by pulling high the Slave Select,SS, line.122ATmega8(L)2486O–AVR–10/04ATmega8(L)When configured as a Master, the SPI interface has no automatic control of the SS line.This must be handled by user software before communication can start.
When this isdone, writing a byte to the SPI Data Register starts the SPI clock generator, and thehardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI interrupt enable bit(SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continueto shift the next byte by writing it into SPDR, or signal the end of packet by pulling highthe Slave Select, SS line. The last incoming byte will be kept in the Buffer Register forlater use.When configured as a Slave, the SPI interface will remain sleeping with MISO tri-statedas long as the SS pin is driven high.
In this state, software may update the contents ofthe SPI Data Register, SPDR, but the data will not be shifted out by incoming clockpulses on the SCK pin until the SS pin is driven low. As one byte has been completelyshifted, the end of Transmission Flag, SPIF is set. If the SPI interrupt enable bit, SPIE,in the SPCR Register is set, an interrupt is requested. The Slave may continue to placenew data to be sent into SPDR before reading the incoming data. The last incoming bytewill be kept in the Buffer Register for later use.Figure 58. SPI Master-Slave InterconnectionMSBMASTERLSBMISOMISOMSB8 BIT SHIFT REGISTERSLAVELSB8 BIT SHIFT REGISTERMOSIMOSISHIFTENABLESPICLOCK GENERATORSCKSSVCCSCKSSThe system is single buffered in the transmit direction and double buffered in the receivedirection.
This means that bytes to be transmitted cannot be written to the SPI DataRegister before the entire shift cycle is completed. When receiving data, however, areceived character must be read from the SPI Data Register before the next characterhas been completely shifted in. Otherwise, the first byte is lost.In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin.
Toensure correct sampling of the clock signal, the frequency of the SPI clock should neverexceed fosc/4.When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins isoverridden according to Table 47. For more details on automatic port overrides, refer to“Alternate Port Functions” on page 54.Table 47. SPI Pin Overrides(1)PinDirection, Master SPIDirection, Slave SPIMOSIUser DefinedInputMISOInputUser DefinedSCKUser DefinedInputSSUser DefinedInputNote:1.
See “Port B Pins Alternate Functions” on page 56 for a detailed description of how todefine the direction of the user defined SPI pins.1232486O–AVR–10/04The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission.
DDR_SPI in the examples must be replaced by the actualData Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCKmust be replaced by the actual data direction bits for these pins. E.g. if MOSI is placedon pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.Assembly Code Example(1)SPI_MasterInit:; Set MOSI and SCK output, all others inputldir17,(1<<DD_MOSI)|(1<<DD_SCK)outDDR_SPI,r17; Enable SPI, Master, set clock rate fck/16ldir17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)outSPCR,r17retSPI_MasterTransmit:; Start transmission of data (r16)outSPDR,r16Wait_Transmit:; Wait for transmission completesbis SPSR,SPIFrjmp Wait_TransmitretC Code Example(1)void SPI_MasterInit(void){/* Set MOSI and SCK output, all others input */DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);/* Enable SPI, Master, set clock rate fck/16 */SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);}void SPI_MasterTransmit(char cData){/* Start transmission */SPDR = cData;/* Wait for transmission complete */while(!(SPSR & (1<<SPIF)));}Note:1241.
The example code assumes that the part specific header file is included.ATmega8(L)2486O–AVR–10/04ATmega8(L)The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.Assembly Code Example(1)SPI_SlaveInit:; Set MISO output, all others inputldir17,(1<<DD_MISO)outDDR_SPI,r17; Enable SPIldir17,(1<<SPE)outSPCR,r17retSPI_SlaveReceive:; Wait for reception completesbis SPSR,SPIFrjmp SPI_SlaveReceive; Read received data and returninr16,SPDRretC Code Example(1)void SPI_SlaveInit(void){/* Set MISO output, all others input */DDR_SPI = (1<<DD_MISO);/* Enable SPI */SPCR = (1<<SPE);}char SPI_SlaveReceive(void){/* Wait for reception complete */while(!(SPSR & (1<<SPIF)));/* Return data register */return SPDR;}Note:1. The example code assumes that the part specific header file is included.1252486O–AVR–10/04SS Pin FunctionalitySlave ModeWhen the SPI is configured as a Slave, the Slave Select (SS) pin is always input.
WhenSS is held low, the SPI is activated, and MISO becomes an output if configured so bythe user. All other pins are inputs. When SS is driven high, all pins are inputs, and theSPI is passive, which means that it will not receive incoming data. Note that the SPIlogic will be reset once the SS pin is driven high.The SS pin is useful for packet/byte synchronization to keep the Slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI Slavewill immediately reset the send and receive logic, and drop any partially received data inthe Shift Register.Master ModeWhen the SPI is configured as a Master (MSTR in SPCR is set), the user can determinethe direction of the SS pin.If SS is configured as an output, the pin is a general output pin which does not affect theSPI system.
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