ATmega8 (961722), страница 22
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This feature allowsOCR2 to be initialized to the same value as TCNT2 without triggering an interrupt whenthe Timer/Counter clock is enabled.Using the Output CompareUnitSince writing TCNT2 in any mode of operation will block all compare matches for onetimer clock cycle, there are risks involved when changing TCNT2 when using the OutputCompare channel, independently of whether the Timer/Counter is running or not. If thevalue written to TCNT2 equals the OCR2 value, the Compare Match will be missed,resulting in incorrect waveform generation.
Similarly, do not write the TCNT2 valueequal to BOTTOM when the counter is downcounting.The setup of the OC2 should be performed before setting the Data Direction Register forthe port pin to output. The easiest way of setting the OC2 value is to use the Force Output Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value evenwhen changing between waveform generation modes.Be aware that the COM21:0 bits are not double buffered together with the comparevalue.
Changing the COM21:0 bits will take effect immediately.106ATmega8(L)2486O–AVR–10/04ATmega8(L)Compare Match OutputUnitThe Compare Output mode (COM21:0) bits have two functions. The waveform generator uses the COM21:0 bits for defining the Output Compare (OC2) state at the nextCompare Match. Also, the COM21:0 bits control the OC2 pin output source. Figure 48shows a simplified schematic of the logic affected by the COM21:0 bit setting.
The I/ORegisters, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of thegeneral I/O Port Control Registers (DDR and PORT) that are affected by the COM21:0bits are shown. When referring to the OC2 state, the reference is for the internal OC2Register, not the OC2 pin.Figure 48. Compare Match Output Unit, SchematicCOMn1COMn0FOCnWaveformGeneratorDQ1OCnDATABUSD0OCnPinQPORTDQDDRclk I/OThe general I/O port function is overridden by the Output Compare (OC2) from thewaveform generator if either of the COM21:0 bits are set.
However, the OC2 pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the portpin. The Data Direction Register bit for the OC2 pin (DDR_OC2) must be set as outputbefore the OC2 value is visible on the pin. The port override function is independent ofthe Waveform Generation mode.The design of the Output Compare Pin logic allows initialization of the OC2 state beforethe output is enabled. Note that some COM21:0 bit settings are reserved for certainmodes of operation.
See “8-bit Timer/Counter Register Description” on page 115.1072486O–AVR–10/04Compare Output Mode andWaveform GenerationThe Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWMmodes. For all modes, setting the COM21:0 = 0 tells the waveform generator that noaction on the OC2 Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 43 on page 116. For fastPWM mode, refer to Table 44 on page 116, and for phase correct PWM refer to Table45 on page 116.A change of the COM21:0 bits state will have effect at the first Compare Match after thebits are written. For non-PWM modes, the action can be forced to have immediate effectby using the FOC2 strobe bits.Modes of OperationThe mode of operation (i.e., the behavior of the Timer/Counter and the Output Comparepins) is defined by the combination of the Waveform Generation mode (WGM21:0) andCompare Output mode (COM21:0) bits.
The Compare Output mode bits do not affectthe counting sequence, while the Waveform Generation mode bits do. The COM21:0bits control whether the PWM output generated should be inverted or not (inverted ornon-inverted PWM). For non-PWM modes the COM21:0 bits control whether the outputshould be set, cleared, or toggled at a Compare Match (see “Compare Match OutputUnit” on page 107).For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 113.Normal ModeThe simplest mode of operation is the Normal mode (WGM21:0 = 0).
In this mode thecounting direction is always up (incrementing), and no counter clear is performed. Thecounter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and thenrestarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag(TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. TheTOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared.However, combined with the timer overflow interrupt that automatically clears the TOV2Flag, the timer resolution can be increased by software. There are no special cases toconsider in the Normal mode, a new counter value can be written anytime.The Output Compare unit can be used to generate interrupts at some given time.
Usingthe Output Compare to generate waveforms in Normal mode is not recommended,since this will occupy too much of the CPU time.108ATmega8(L)2486O–AVR–10/04ATmega8(L)Clear Timer on CompareMatch (CTC) ModeIn Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used tomanipulate the counter resolution. In CTC mode the counter is cleared to zero when thecounter value (TCNT2) matches the OCR2.
The OCR2 defines the top value for thecounter, hence also its resolution. This mode allows greater control of the CompareMatch output frequency. It also simplifies the operation of counting external events.The timing diagram for the CTC mode is shown in Figure 49. The counter value(TCNT2) increases until a Compare Match occurs between TCNT2 and OCR2, and thencounter (TCNT2) is cleared.Figure 49. CTC Mode, Timing DiagramOCn Interrupt Flag SetTCNTnOCn(Toggle)Period(COMn1:0 = 1)1234An interrupt can be generated each time the counter value reaches the TOP value byusing the OCF2 Flag. If the interrupt is enabled, the interrupt handler routine can beused for updating the TOP value.
However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done withcare since the CTC mode does not have the double buffering feature. If the new valuewritten to OCR2 is lower than the current value of TCNT2, the counter will miss theCompare Match. The counter will then have to count to its maximum value (0xFF) andwrap around starting at 0x00 before the Compare Match can occur.For generating a waveform output in CTC mode, the OC2 output can be set to toggle itslogical level on each Compare Match by setting the Compare Output mode bits to togglemode (COM21:0 = 1). The OC2 value will not be visible on the port pin unless the datadirection for the pin is set to output.
The waveform generated will have a maximum frequency of fOC2 = fclk_I/O/2 when OCR2 is set to zero (0x00). The waveform frequency isdefined by the following equation:f clk_I/Of OCn = ---------------------------------------------2 ⋅ N ⋅ ( 1 + OCRn )The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).As for the Normal mode of operation, the TOV2 Flag is set in the same timer clock cyclethat the counter counts from MAX to 0x00.1092486O–AVR–10/04Fast PWM ModeThe fast Pulse Width Modulation or fast PWM mode (WGM21:0 = 3) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWMoption by its single-slope operation. The counter counts from BOTTOM to MAX thenrestarts from BOTTOM.
In non-inverting Compare Output mode, the Output Compare(OC2) is cleared on the Compare Match between TCNT2 and OCR2, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match andcleared at BOTTOM. Due to the single-slope operation, the operating frequency of thefast PWM mode can be twice as high as the phase correct PWM mode that uses dualslope operation. This high frequency makes the fast PWM mode well suited for powerregulation, rectification, and DAC applications.
High frequency allows physically smallsized external components (coils, capacitors), and therefore reduces total system cost.In fast PWM mode, the counter is incremented until the counter value matches the MAXvalue. The counter is then cleared at the following timer clock cycle. The timing diagramfor the fast PWM mode is shown in Figure 50.
The TCNT2 value is in the timing diagramshown as a histogram for illustrating the single-slope operation. The diagram includesnon-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2slopes represent compare matches between OCR2 and TCNT2.Figure 50. Fast PWM Mode, Timing DiagramOCRn Interrupt Flag SetOCRn UpdateandTOVn Interrupt Flag SetTCNTnOCn(COMn1:0 = 2)OCn(COMn1:0 = 3)Period1234567The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. Ifthe interrupt is enabled, the interrupt handler routine can be used for updating the compare value.In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC2pin. Setting the COM21:0 bits to 2 will produce a non-inverted PWM and an invertedPWM output can be generated by setting the COM21:0 to 3 (see Table 44 on page 116).The actual OC2 value will only be visible on the port pin if the data direction for the portpin is set as output.
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