ATmega8 (961722), страница 27
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This is done byallowing the received data to remain in the serial Shift Register (see Figure 61) if theBuffer Registers are full, until a new start bit is detected. The USART is thereforemore resistant to Data OverRun (DOR) error conditions.The following control bits have changed name, but have same functionality and registerlocation:Clock Generation•CHR9 is changed to UCSZ2.•OR is changed to DOR.The clock generation logic generates the base clock for the Transmitter and Receiver.The USART supports four modes of clock operation: normal asynchronous, doublespeed asynchronous, Master synchronous and Slave Synchronous mode. The UMSELbit in USART Control and Status Register C (UCSRC) selects between asynchronousand synchronous operation.
Double speed (Asynchronous mode only) is controlled bythe U2X found in the UCSRA Register. When using Synchronous mode (UMSEL = 1),the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clocksource is internal (Master mode) or external (Slave mode). The XCK pin is only activewhen using Synchronous mode.Figure 62 shows a block diagram of the clock generation logic.1312486O–AVR–10/04Figure 62. Clock Generation Logic, Block DiagramUBRRU2XfoscPrescalingDown-CounterUBRR+1/2/4/2010OSCDDR_XCKxckiXCKPinSyncRegisterEdgeDetectorUCPOLDDR_XCK0UMSEL1xckotxclk110rxclkSignal description:Internal Clock Generation –The Baud Rate GeneratortxclkTransmitter clock. (Internal Signal)rxclkReceiver base clock.
(Internal Signal)xckiInput from XCK pin (internal Signal). Used for synchronous slave operation.xckoClock output to XCK pin (Internal Signal). Used for synchronous masteroperation.foscXTAL pin frequency (System Clock).Internal clock generation is used for the asynchronous and the Synchronous Mastermodes of operation. The description in this section refers to Figure 62.The USART Baud Rate Register (UBRR) and the down-counter connected to it functionas a programmable prescaler or baud rate generator. The down-counter, running at system clock (fosc), is loaded with the UBRR value each time the counter has counteddown to zero or when the UBRRL Register is written.
A clock is generated each time thecounter reaches zero. This clock is the baud rate generator clock output (=fosc/(UBRR+1)). The Transmitter divides the baud rate generator clock output by 2, 8,or 16 depending on mode. The baud rate generator output is used directly by theReceiver’s clock and data recovery units. However, the recovery units use a statemachine that uses 2, 8, or 16 states depending on mode set by the state of the UMSEL,U2X and DDR_XCK bits.Table 52 contains equations for calculating the baud rate (in bits per second) and forcalculating the UBRR value for each mode of operation using an internally generatedclock source.132ATmega8(L)2486O–AVR–10/04ATmega8(L)Table 52. Equations for Calculating Baud Rate Register SettingEquation for CalculatingBaud Rate(1)Equation for CalculatingUBRR ValueAsynchronous Normal mode(U2X = 0)f OSCBAUD = -------------------------------------16 ( UBRR + 1 )f OSCUBRR = -----------------------–116BAUDAsynchronous Double SpeedMode (U2X = 1)f OSCBAUD = ---------------------------------8 ( UBRR + 1 )f OSCUBRR = -------------------–18BAUDSynchronous Master Modef OSCBAUD = ---------------------------------2 ( UBRR + 1 )f OSCUBRR = -------------------–12BAUDOperating ModeNote:1.
The baud rate is defined to be the transfer rate in bit per second (bps).BAUD Baud rate (in bits per second, bps)fOSCSystem Oscillator clock frequencyUBRR Contents of the UBRRH and UBRRL Registers, (0 - 4095)Some examples of UBRR values for some system clock frequencies are found in Table60 (see page 156).Double Speed Operation(U2X)The transfer rate can be doubled by setting the U2X bit in UCSRA.
Setting this bit onlyhas effect for the asynchronous operation. Set this bit to zero when using synchronousoperation.Setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectivelydoubling the transfer rate for asynchronous communication. Note however that theReceiver will in this case only use half the number of samples (reduced from 16 to 8) fordata sampling and clock recovery, and therefore a more accurate baud rate setting andsystem clock are required when this mode is used. For the Transmitter, there are nodownsides.External ClockExternal clocking is used by the Synchronous Slave modes of operation.
The description in this section refers to Figure 62 for details.External clock input from the XCK pin is sampled by a synchronization register to minimize the chance of meta-stability. The output from the synchronization register mustthen pass through an edge detector before it can be used by the Transmitter andReceiver.
This process introduces a two CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation:f OSCf XCK < ----------4Note that fosc depends on the stability of the system clock source.
It is therefore recommended to add some margin to avoid possible loss of data due to frequency variations.1332486O–AVR–10/04Synchronous Clock Operation When Synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clockinput (Slave) or clock output (Master). The dependency between the clock edges anddata sampling or data change is the same.
The basic principle is that data input (onRxD) is sampled at the opposite XCK clock edge of the edge the data output (TxD) ischanged.Figure 63. Synchronous Mode XCK TimingUCPOL = 1XCKRxD / TxDSampleUCPOL = 0XCKRxD / TxDSampleThe UCPOL bit UCRSC selects which XCK clock edge is used for data sampling andwhich is used for data change. As Figure 63 shows, when UCPOL is zero the data willbe changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, thedata will be changed at falling XCK edge and sampled at rising XCK edge.Frame FormatsA serial frame is defined to be one character of data bits with synchronization bits (startand stop bits), and optionally a parity bit for error checking.
The USART accepts all 30combinations of the following as valid frame formats:•1 start bit•5, 6, 7, 8, or 9 data bits•no, even or odd parity bit•1 or 2 stop bitsA frame starts with the start bit followed by the least significant data bit. Then the nextdata bits, up to a total of nine, are succeeding, ending with the most significant bit. Ifenabled, the parity bit is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can be directly followed by a new frame, or thecommunication line can be set to an idle (high) state. Figure 64 illustrates the possiblecombinations of the frame formats. Bits inside brackets are optional.Figure 64.
Frame FormatsFRAME(IDLE)134St01234StStart bit, always low.(n)Data bits (0 to 8).PParity bit. Can be odd or even.[5][6][7][8][P]Sp1 [Sp2](St / IDLE)ATmega8(L)2486O–AVR–10/04ATmega8(L)SpStop bit, always high.IDLENo transfers on the communication line (RxD or TxD). An IDLE line must behigh.The frame format used by the USART is set by the UCSZ2:0, UPM1:0 and USBS bits inUCSRB and UCSRC.
The Receiver and Transmitter use the same setting. Note thatchanging the setting of any of these bits will corrupt all ongoing communication for boththe Receiver and Transmitter.The USART Character SiZe (UCSZ2:0) bits select the number of data bits in the frame.The USART Parity mode (UPM1:0) bits enable and set the type of parity bit. The selection between one or two stop bits is done by the USART Stop Bit Select (USBS) bit. TheReceiver ignores the second stop bit. An FE (Frame Error) will therefore only bedetected in the cases where the first stop bit is zero.Parity Bit CalculationThe parity bit is calculated by doing an exclusive-or of all the data bits.
If odd parity isused, the result of the exclusive or is inverted. The relation between the parity bit anddata bits is as follows:P even = d n – 1 ⊕ … ⊕ d 3 ⊕ d 2 ⊕ d 1 ⊕ d 0 ⊕ 0P odd = d n – 1 ⊕ … ⊕ d 3 ⊕ d 2 ⊕ d 1 ⊕ d 0 ⊕ 1PevenParity bit using even parity.PoddParity bit using odd parity.dnData bit n of the character.If used, the parity bit is located between the last data bit and first stop bit of a serialframe.USART InitializationThe USART has to be initialized before any communication can take place. The initialization process normally consists of setting the baud rate, setting frame format andenabling the Transmitter or the Receiver depending on the usage.
For interrupt drivenUSART operation, the Global Interrupt Flag should be cleared (and interrupts globallydisabled) when doing the initialization.Before doing a re-initialization with changed baud rate or frame format, be sure thatthere are no ongoing transmissions during the period the registers are changed. TheTXC Flag can be used to check that the Transmitter has completed all transfers, and theRXC Flag can be used to check that there are no unread data in the receive buffer.
Notethat the TXC Flag must be cleared before each transmission (before UDR is written) if itis used for this purpose.The following simple USART initialization code examples show one assembly and oneC function that are equal in functionality.
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