ATmega8 (961722), страница 31
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The example code assumes that the part specific header file is included.As the code examples illustrate, write accesses of the two registers are relatively unaffected of the sharing of I/O location.1492486O–AVR–10/04Read AccessDoing a read access to the UBRRH or the UCSRC Register is a more complex operation. However, in most applications, it is rarely necessary to read any of these registers.The read access is controlled by a timed sequence. Reading the I/O location oncereturns the UBRRH Register contents. If the register location was read in previous system clock cycle, reading the register in the current clock cycle will return the UCSRCcontents.
Note that the timed sequence for reading the UCSRC is an atomic operation.Interrupts must therefore be controlled (e.g., by disabling interrupts globally) during theread operation.The following code example shows how to read the UCSRC Register contents.Assembly Code Example(1)USART_ReadUCSRC:; Read UCSRCin r16,UBRRHin r16,UCSRCretC Code Example(1)unsigned char USART_ReadUCSRC( void ){unsigned char ucsrc;/* Read UCSRC */ucsrc = UBRRH;ucsrc = UCSRC;return ucsrc;}Note:1. The example code assumes that the part specific header file is included.The assembly code example returns the UCSRC value in r16.Reading the UBRRH contents is not an atomic operation and therefore it can be read asan ordinary register, as long as the previous instruction did not access the registerlocation.USART RegisterDescriptionUSART I/O Data Register –UDRBit76543210RXB[7:0]UDR (Read)TXB[7:0]UDR (Write)Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000The USART Transmit Data Buffer Register and USART Receive Data Buffer Registersshare the same I/O address referred to as USART Data Register or UDR.
The TransmitData Buffer Register (TXB) will be the destination for data written to the UDR Registerlocation. Reading the UDR Register location will return the contents of the Receive DataBuffer Register (RXB).For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitterand set to zero by the Receiver.150ATmega8(L)2486O–AVR–10/04ATmega8(L)The transmit buffer can only be written when the UDRE Flag in the UCSRA Register isset. Data written to UDR when the UDRE Flag is not set, will be ignored by the USARTTransmitter. When data is written to the transmit buffer, and the Transmitter is enabled,the Transmitter will load the data into the Transmit Shift Register when the Shift Registeris empty. Then the data will be serially transmitted on the TxD pin.The receive buffer consists of a two level FIFO. The FIFO will change its state wheneverthe receive buffer is accessed.
Due to this behavior of the receive buffer, do not useRead-Modify-Write instructions (SBI and CBI) on this location. Be careful when using bittest instructions (SBIC and SBIS), since these also will change the state of the FIFO.USART Control and StatusRegister A – UCSRABit76543210RXCTXCUDREFEDORPEU2XMPCMRead/WriteRR/WRRRRR/WR/WInitial Value00100000UCSRA• Bit 7 – RXC: USART Receive CompleteThis flag bit is set when there are unread data in the receive buffer and cleared when thereceive buffer is empty (i.e. does not contain any unread data). If the Receiver is disabled, the receive buffer will be flushed and consequently the RXC bit will become zero.The RXC Flag can be used to generate a Receive Complete interrupt (see description ofthe RXCIE bit).• Bit 6 – TXC: USART Transmit CompleteThis flag bit is set when the entire frame in the Transmit Shift Register has been shiftedout and there are no new data currently present in the transmit buffer (UDR).
The TXCFlag bit is automatically cleared when a transmit complete interrupt is executed, or it canbe cleared by writing a one to its bit location. The TXC Flag can generate a TransmitComplete interrupt (see description of the TXCIE bit).• Bit 5 – UDRE: USART Data Register EmptyThe UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. IfUDRE is one, the buffer is empty, and therefore ready to be written. The UDRE Flag cangenerate a Data Register Empty interrupt (see description of the UDRIE bit).UDRE is set after a reset to indicate that the Transmitter is ready.• Bit 4 – FE: Frame ErrorThis bit is set if the next character in the receive buffer had a Frame Error when received(i.e., when the first stop bit of the next character in the receive buffer is zero). This bit isvalid until the receive buffer (UDR) is read.
The FE bit is zero when the stop bit ofreceived data is one. Always set this bit to zero when writing to UCSRA.• Bit 3 – DOR: Data OverRunThis bit is set if a Data OverRun condition is detected. A Data OverRun occurs when thereceive buffer is full (two characters), it is a new character waiting in the Receive ShiftRegister, and a new start bit is detected. This bit is valid until the receive buffer (UDR) isread.
Always set this bit to zero when writing to UCSRA.• Bit 2 – PE: Parity ErrorThis bit is set if the next character in the receive buffer had a Parity Error when receivedand the parity checking was enabled at that point (UPM1 = 1). This bit is valid until thereceive buffer (UDR) is read. Always set this bit to zero when writing to UCSRA.• Bit 1 – U2X: Double the USART transmission speed1512486O–AVR–10/04This bit only has effect for the asynchronous operation.
Write this bit to zero when usingsynchronous operation.Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication.• Bit 0 – MPCM: Multi-processor Communication ModeThis bit enables the Multi-processor Communication mode. When the MPCM bit is written to one, all the incoming frames received by the USART Receiver that do not containaddress information will be ignored.
The Transmitter is unaffected by the MPCM setting.For more detailed information see “Multi-processor Communication Mode” on page 148.USART Control and StatusRegister B – UCSRBBit76543210RXCIETXCIEUDRIERXENTXENUCSZ2RXB8TXB8Read/WriteR/WR/WR/WR/WR/WR/WRR/WInitial Value00000000UCSRB• Bit 7 – RXCIE: RX Complete Interrupt EnableWriting this bit to one enables interrupt on the RXC Flag.
A USART Receive Completeinterrupt will be generated only if the RXCIE bit is written to one, the Global InterruptFlag in SREG is written to one and the RXC bit in UCSRA is set.• Bit 6 – TXCIE: TX Complete Interrupt EnableWriting this bit to one enables interrupt on the TXC Flag. A USART Transmit Completeinterrupt will be generated only if the TXCIE bit is written to one, the Global InterruptFlag in SREG is written to one and the TXC bit in UCSRA is set.• Bit 5 – UDRIE: USART Data Register Empty Interrupt EnableWriting this bit to one enables interrupt on the UDRE Flag.
A Data Register Empty interrupt will be generated only if the UDRIE bit is written to one, the Global Interrupt Flag inSREG is written to one and the UDRE bit in UCSRA is set.• Bit 4 – RXEN: Receiver EnableWriting this bit to one enables the USART Receiver. The Receiver will override normalport operation for the RxD pin when enabled. Disabling the Receiver will flush thereceive buffer invalidating the FE, DOR and PE Flags.• Bit 3 – TXEN: Transmitter EnableWriting this bit to one enables the USART Transmitter. The Transmitter will override normal port operation for the TxD pin when enabled.
The disabling of the Transmitter(writing TXEN to zero) will not become effective until ongoing and pending transmissions are completed (i.e., when the Transmit Shift Register and Transmit Buffer Registerdo not contain data to be transmitted). When disabled, the Transmitter will no longeroverride the TxD port.• Bit 2 – UCSZ2: Character SizeThe UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits(Character Size) in a frame the Receiver and Transmitter use.• Bit 1 – RXB8: Receive Data Bit 8RXB8 is the ninth data bit of the received character when operating with serial frameswith nine data bits. Must be read before reading the low bits from UDR.• Bit 0 – TXB8: Transmit Data Bit 8152ATmega8(L)2486O–AVR–10/04ATmega8(L)TXB8 is the ninth data bit in the character to be transmitted when operating with serialframes with nine data bits.
Must be written before writing the low bits to UDR.USART Control and StatusRegister C – UCSRCBit76543210URSELUMSELUPM1UPM0USBSUCSZ1UCSZ0UCPOLRead/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value10000110UCSRCThe UCSRC Register shares the same I/O location as the UBRRH Register. See the“Accessing UBRRH/UCSRC Registers” on page 149 section which describes how toaccess this register.• Bit 7 – URSEL: Register SelectThis bit selects between accessing the UCSRC or the UBRRH Register.
It is read asone when reading UCSRC. The URSEL must be one when writing the UCSRC.• Bit 6 – UMSEL: USART Mode SelectThis bit selects between Asynchronous and Synchronous mode of operation.Table 55. UMSEL Bit SettingsUMSELMode0Asynchronous Operation1Synchronous Operation1532486O–AVR–10/04• Bit 5:4 – UPM1:0: Parity ModeThese bits enable and set type of Parity Generation and Check. If enabled, the Transmitter will automatically generate and send the parity of the transmitted data bits withineach frame.
The Receiver will generate a parity value for the incoming data and compare it to the UPM0 setting. If a mismatch is detected, the PE Flag in UCSRA will be set.Table 56. UPM Bits SettingsUPM1UPM0Parity Mode00Disabled01Reserved10Enabled, Even Parity11Enabled, Odd Parity• Bit 3 – USBS: Stop Bit SelectThis bit selects the number of stop bits to be inserted by the trAnsmitter. The Receiverignores this setting.Table 57. USBS Bit SettingsUSBSStop Bit(s)01-bit12-bit• Bit 2:1 – UCSZ1:0: Character SizeThe UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits(Character Size) in a frame the Receiver and Transmitter use.Table 58.
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