ATmega8 (961722), страница 33
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The only exceptionto this rule is for generating start and stop conditions.Figure 69. Data ValiditySDASCLData StableData StableData ChangeSTART and STOP ConditionsThe Master initiates and terminates a data transmission. The transmission is initiatedwhen the Master issues a START condition on the bus, and it is terminated when theMaster issues a STOP condition. Between a START and a STOP condition, the bus isconsidered busy, and no other master should try to seize control of the bus. A specialcase occurs when a new START condition is issued between a START and STOP condition. This is referred to as a REPEATED START condition, and is used when theMaster wishes to initiate a new transfer without relinquishing control of the bus.
After aREPEATED START, the bus is considered busy until the next STOP. This is identical tothe START behavior, and therefore START is used to describe both START andREPEATED START for the remainder of this datasheet, unless otherwise noted. Asdepicted below, START and STOP conditions are signalled by changing the level of theSDA line when the SCL line is high.1612486O–AVR–10/04Figure 70. START, REPEATED START and STOP conditionsSDASCLSTARTAddress Packet FormatSTOPREPEATED STARTSTARTSTOPAll address packets transmitted on the TWI bus are 9 bits long, consisting of 7 addressbits, one READ/WRITE control bit and an acknowledge bit.
If the READ/WRITE bit isset, a read operation is to be performed, otherwise a write operation should be performed. When a Slave recognizes that it is being addressed, it should acknowledge bypulling SDA low in the ninth SCL (ACK) cycle. If the addressed Slave is busy, or forsome other reason can not service the Master’s request, the SDA line should be lefthigh in the ACK clock cycle. The Master can then transmit a STOP condition, or aREPEATED START condition to initiate a new transmission. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W,respectively.The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call.When a general call is issued, all slaves should respond by pulling the SDA line low inthe ACK cycle.
A general call is used when a Master wishes to transmit the same message to several slaves in the system. When the general call address followed by a Writebit is transmitted on the bus, all slaves set up to acknowledge the general call will pullthe SDA line low in the ack cycle. The following data packets will then be received by allthe slaves that acknowledged the general call. Note that transmitting the general calladdress followed by a Read bit is meaningless, as this would cause contention if severalslaves started transmitting different data.All addresses of the format 1111 xxx should be reserved for future purposes.Figure 71. Address Packet FormatAddr MSBAddr LSBR/WACK789SDASCL12START162ATmega8(L)2486O–AVR–10/04ATmega8(L)Data Packet FormatAll data packets transmitted on the TWI bus are nine bits long, consisting of one databyte and an acknowledge bit.
During a data transfer, the Master generates the clock andthe START and STOP conditions, while the Receiver is responsible for acknowledgingthe reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA linelow during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has received the last byte, or for some reason cannot receiveany more bytes, it should inform the Transmitter by sending a NACK after the final byte.The MSB of the data byte is transmitted first.Figure 72. Data Packet FormatData MSBData LSBACK89AggregateSDASDA fromTransmitterSDA fromReceiverSCL fromMaster127SLA+R/WCombining Address and DataPackets into a TransmissionSTOP, REPEATEDSTART or NextData ByteData ByteA transmission basically consists of a START condition, a SLA+R/W, one or more datapackets and a STOP condition.
An empty message, consisting of a START followed bya STOP condition, is illegal. Note that the Wired-ANDing of the SCL line can be used toimplement handshaking between the Master and the Slave. The Slave can extend theSCL low period by pulling the SCL line low. This is useful if the clock speed set up by theMaster is too fast for the Slave, or the Slave needs extra time for processing betweenthe data transmissions. The Slave extending the SCL low period will not affect the SCLhigh period, which is determined by the Master. As a consequence, the Slave canreduce the TWI data transfer speed by prolonging the SCL duty cycle.Figure 73 shows a typical data transmission.
Note that several data bytes can be transmitted between the SLA+R/W and the STOP condition, depending on the softwareprotocol implemented by the application software.Figure 73. Typical Data TransmissionAddr MSBAddr LSBR/WACKData MSB7891Data LSBACK89SDASCL1START2SLA+R/W27Data ByteSTOP1632486O–AVR–10/04Multi-master BusThe TWI protocol allows bus systems with several masters. Special concerns haveSystems, Arbitration and been taken in order to ensure that transmissions will proceed as normal, even if two ormore masters initiate a transmission at the same time. Two problems arise in multi-masSynchronizationter systems:•An algorithm must be implemented allowing only one of the masters to complete thetransmission. All other masters should cease transmission when they discover thatthey have lost the selection process. This selection process is called arbitration.When a contending master discovers that it has lost the arbitration process, itshould immediately switch to Slave mode to check whether it is being addressed bythe winning master.
The fact that multiple masters have started transmission at thesame time should not be detectable to the slaves, i.e. the data being transferred onthe bus must not be corrupted.•Different masters may use different SCL frequencies. A scheme must be devised tosynchronize the serial clocks from all masters, in order to let the transmissionproceed in a lockstep fashion.
This will facilitate the arbitration process.The wired-ANDing of the bus lines is used to solve both these problems. The serialclocks from all masters will be wired-ANDed, yielding a combined clock with a highperiod equal to the one from the Master with the shortest high period.
The low period ofthe combined clock is equal to the low period of the Master with the longest low period.Note that all masters listen to the SCL line, effectively starting to count their SCL highand low time-out periods when the combined SCL line goes high or low, respectively.Figure 74. SCL Synchronization Between Multiple MastersTA lowTA highSCL fromMaster ASCL fromMaster BSCL BusLineTBlowMasters StartCounting Low PeriodTBhighMasters StartCounting High PeriodArbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the Masterhad output, it has lost the arbitration. Note that a Master can only lose arbitration when itoutputs a high SDA value while another Master outputs a low value.
The losing Mastershould immediately go to Slave mode, checking if it is being addressed by the winningMaster. The SDA line should be left high, but losing masters are allowed to generate aclock signal until the end of the current data or address packet. Arbitration will continueuntil only one Master remains, and this may take many bits. If several masters are tryingto address the same Slave, arbitration will continue into the data packet.164ATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 75. Arbitration Between Two MastersSTARTSDA fromMaster AMaster A LosesArbitration, SDAA SDASDA fromMaster BSDA LineSynchronizedSCL LineNote that arbitration is not allowed between:•A REPEATED START condition and a data bit.•A STOP condition and a data bit.•A REPEATED START and a STOP condition.It is the user software’s responsibility to ensure that these illegal arbitration conditionsnever occur.
This implies that in multi-master systems, all data transfers must use thesame composition of SLA+R/W and data packets. In other words: All transmissionsmust contain the same number of data packets, otherwise the result of the arbitration isundefined.1652486O–AVR–10/04Overview of the TWIModuleThe TWI module is comprised of several submodules, as shown in Figure 76.
All registers drawn in a thick line are accessible through the AVR data bus.Figure 76. Overview of the TWI ModuleSlew-rateControlSDASpikeFilterSlew-rateControlSpikeFilterBus Interface UnitSTART / STOPControlSpike SuppressionArbitration detectionAddress/Data ShiftRegister (TWDR)Address Match UnitAddress Register(TWAR)Address ComparatorSCL and SDA Pins166Bit Rate GeneratorPrescalerBit Rate Register(TWBR)AckControl UnitStatus Register(TWSR)Control Register(TWCR)State Machine andStatus controlTWI UnitSCLThese pins interface the AVR TWI with the rest of the MCU system. The output driverscontain a slew-rate limiter in order to conform to the TWI specification. The input stagescontain a spike suppression unit removing spikes shorter than 50 ns.
Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding tothe SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can insome systems eliminate the need for external ones.ATmega8(L)2486O–AVR–10/04ATmega8(L)Bit Rate Generator UnitThis unit controls the period of SCL when operating in a Master mode. The SCL periodis controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits inthe TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the CPU clock frequency in the Slave must be at least 16 times higherthan the SCL frequency.
Note that slaves may prolong the SCL low period, therebyreducing the average TWI bus clock period. The SCL frequency is generated accordingto the following equation:CPU Clock frequencySCL frequency = ---------------------------------------------------------TWPS16 + 2(TWBR) ⋅ 4•TWBR = Value of the TWI Bit Rate Register.•TWPS = Value of the prescaler bits in the TWI Status Register.Note:Bus Interface UnitTWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than10, the Master may produce an incorrect output on SDA and SCL for the reminder of thebyte. The problem occurs when operating the TWI in Master mode, sending Start + SLA+ R/W to a Slave (a Slave does not need to be connected to the bus for the condition tohappen).This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and Arbitration detection hardware.
The TWDR contains the address or databytes to be transmitted, or the address or data bytes received. In addition to the 8-bitTWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to betransmitted or received. This (N)ACK Register is not directly accessible by the application software. However, when receiving, it can be set or cleared by manipulating theTWI Control Register (TWCR).
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