ATmega8 (961722), страница 37
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Status codes for Master Receiver ModeStatus Code(TWSR)Prescaler Bitsare 0Application Software ResponseStatus of the Two-wire SerialBus and Two-wire Serial Interface HardwareTo TWCRTo/from TWDRTWINTTWEA0x08A START condition has beentransmittedLoad SLA+R001XSLA+R will be transmittedACK or NOT ACK will be received0x10A repeated START conditionhas been transmittedLoad SLA+R or001XLoad SLA+W001XSLA+R will be transmittedACK or NOT ACK will be receivedSLA+W will be transmittedLogic will switch to Master Transmitter modeNo TWDR action or001XNo TWDR action101XNo TWDR action or0010No TWDR action0011No TWDR action orNo TWDR action or100111XXNo TWDR action111X00x380x400x48Arbitration lost in SLA+R or NOTACK bitSLA+R has been transmitted;ACK has been receivedSLA+R has been transmitted;NOT ACK has been receivedSTASTO0x50Data byte has been received;ACK has been returnedRead data byte or001Read data byte00110x58Data byte has been received;NOT ACK has been returnedRead data byte orRead data byte or100111XXRead data byte111X180Next Action Taken by TWI HardwareTwo-wire Serial Bus will be released and not addressedSlave mode will be enteredA START condition will be transmitted when the busbecomes freeData byte will be received and NOT ACK will bereturnedData byte will be received and ACK will be returnedRepeated START will be transmittedSTOP condition will be transmitted and TWSTO Flag willbe resetSTOP condition followed by a START condition will betransmitted and TWSTO Flag will be resetData byte will be received and NOT ACK will bereturnedData byte will be received and ACK will be returnedRepeated START will be transmittedSTOP condition will be transmitted and TWSTO Flag willbe resetSTOP condition followed by a START condition will betransmitted and TWSTO Flag will be resetATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 81.
Formats and States in the Master Receiver ModeMRSuccessfullreceptionfrom a slavereceiverSSLARADATAA$40$08DATAA$50P$58Next transferstarted with arepeated startconditionRSSLAR$10Not acknowledgereceived after theslave addressAWP$48MTArbitration lost in slaveaddress or data byteOther mastercontinuesA or AA$38Arbitration lost andaddressed as slave$38Other mastercontinuesA$68From master to slave$78To correspondingstates in slave mode$B0DATAAFrom slave to masterSlave Receiver ModeOther mastercontinuesnAny number of data bytesand their associated acknowledge bitsThis number (contained in TWSR) correspondsto a defined state of the Two-Wire Serial Bus. Theprescaler bits are zero or masked to zeroIn the Slave Receiver mode, a number of data bytes are received from a Master Transmitter (see Figure 82).
All the status codes mentioned in this section assume that theprescaler bits are zero or are masked to zero.Figure 82. Data transfer in Slave Receiver modeVCCDevice 1Device 2SLAVERECEIVERMASTERTRANSMITTERDevice 3........Device nR1R2SDASCLTo initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:TWARvalueTWA6TWA5TWA4TWA3TWA2TWA1TWA0TWGCEDevice’s Own Slave Address1812486O–AVR–10/04The upper 7 bits are the address to which the Two-wire Serial Interface will respondwhen addressed by a Master. If the LSB is set, the TWI will respond to the general calladdress (0x00), otherwise it will ignore the general call address.TWCRvalueTWINTTWEATWSTATWSTOTWWCTWEN–TWIE0100010XTWEN must be written to one to enable the TWI.
The TWEA bit must be written to oneto enable the acknowledgement of the device’s own slave address or the general calladdress. TWSTA and TWSTO must be written to zero.When TWAR and TWCR have been initialized, the TWI waits until it is addressed by itsown slave address (or the general call address if enabled) followed by the data directionbit. If the direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST modeis entered. After its own slave address and the write bit have been received, the TWINTFlag is set and a valid status code can be read from TWSR.
The status code is used todetermine the appropriate software action. The appropriate action to be taken for eachstatus code is detailed in Table 68. The Slave Receiver mode may also be entered ifarbitration is lost while the TWI is in the Master mode (see states 0x68 and 0x78).If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”)to SDA after the next received data byte. This can be used to indicate that the Slave isnot able to receive any more bytes. While TWEA is zero, the TWI does not acknowledgeits own slave address.
However, the Two-wire Serial Bus is still monitored and addressrecognition may resume at any time by setting TWEA. This implies that the TWEA bitmay be used to temporarily isolate the TWI from the Two-wire Serial Bus.In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If theTWEA bit is set, the interface can still acknowledge its own slave address or the generalcall address by using the Two-wire Serial Bus clock as a clock source.
The part will thenwake up from sleep and the TWI will hold the SCL clock low during the wake up anduntil the TWINT Flag is cleared (by writing it to one). Further data reception will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR isset up with a long start-up time, the SCL line may be held low for a long time, blockingother data transmissions.Note that the Two-wire Serial Interface Data Register – TWDR does not reflect the lastbyte present on the bus when waking up from these Sleep modes.182ATmega8(L)2486O–AVR–10/04ATmega8(L)Table 68. Status Codes for Slave Receiver ModeStatus Code(TWSR)Prescaler Bitsare 0Application Software ResponseStatus of the Two-wire Serial Busand Two-wire Serial InterfaceHardwareTo TWCRTo/from TWDRSTASTOTWINTTWEANo TWDR action orX0100x60Own SLA+W has been received;ACK has been returnedNo TWDR actionX0110x68Arbitration lost in SLA+R/W asMaster; own SLA+W has beenreceived; ACK has been returnedNo TWDR action orX010No TWDR actionX0110x70General call address has beenreceived; ACK has been returnedNo TWDR action orX010No TWDR actionX0110x78Arbitration lost in SLA+R/W asMaster; General call address hasbeen received; ACK has beenreturnedNo TWDR action orX010No TWDR actionX0110x80Previously addressed with ownSLA+W; data has been received;ACK has been returnedRead data byte orX010Read data byteX0110x88Previously addressed with ownSLA+W; data has been received;NOT ACK has been returnedRead data byte or0010Read data byte or0011Read data byte or1010Read data byte10110x90Previously addressed withgeneral call; data has been received; ACK has been returnedRead data byte orX010Read data byteX0110x98Previously addressed withgeneral call; data has beenreceived; NOT ACK has beenreturnedRead data byte or0010Read data byte or0011Read data byte or1010Read data byte1011No action00100011101010110xA0A STOP condition or repeatedSTART condition has beenreceived while still addressed asSlaveNext Action Taken by TWI HardwareData byte will be received and NOT ACK will bereturnedData byte will be received and ACK will be returnedData byte will be received and NOT ACK will bereturnedData byte will be received and ACK will be returnedData byte will be received and NOT ACK will bereturnedData byte will be received and ACK will be returnedData byte will be received and NOT ACK will bereturnedData byte will be received and ACK will be returnedData byte will be received and NOT ACK will bereturnedData byte will be received and ACK will be returnedSwitched to the not addressed Slave mode;no recognition of own SLA or GCASwitched to the not addressed Slave mode;own SLA will be recognized;GCA will be recognized if TWGCE = “1”Switched to the not addressed Slave mode;no recognition of own SLA or GCA;a START condition will be transmitted when the busbecomes freeSwitched to the not addressed Slave mode;own SLA will be recognized;GCA will be recognized if TWGCE = “1”;a START condition will be transmitted when the busbecomes freeData byte will be received and NOT ACK will bereturnedData byte will be received and ACK will be returnedSwitched to the not addressed Slave mode;no recognition of own SLA or GCASwitched to the not addressed Slave mode;own SLA will be recognized;GCA will be recognized if TWGCE = “1”Switched to the not addressed Slave mode;no recognition of own SLA or GCA;a START condition will be transmitted when the busbecomes freeSwitched to the not addressed Slave mode;own SLA will be recognized;GCA will be recognized if TWGCE = “1”;a START condition will be transmitted when the busbecomes freeSwitched to the not addressed Slave mode;no recognition of own SLA or GCASwitched to the not addressed Slave mode;own SLA will be recognized;GCA will be recognized if TWGCE = “1”Switched to the not addressed Slave mode;no recognition of own SLA or GCA;a START condition will be transmitted when the busbecomes freeSwitched to the not addressed Slave mode;own SLA will be recognized;GCA will be recognized if TWGCE = “1”;a START condition will be transmitted when the busbecomes free1832486O–AVR–10/04Figure 83.
Formats and States in the Slave Receiver ModeReception of the ownslave address and one ormore data bytes. All areacknowledgedSSLAWADATA$60ADATA$80Last data byte receivedis not acknowledgedAP or S$80$A0AP or S$88Arbitration lost as masterand addressed as slaveA$68Reception of the general calladdress and one or more databytesGeneral CallADATA$70ADATA$90Last data byte received isnot acknowledgedAP or S$90$A0AP or S$98Arbitration lost as master andaddressed as slave by general callA$78From master to slaveFrom slave to master184DATAAnAny number of data bytesand their associated acknowledge bitsThis number (contained in TWSR) correspondsto a defined state of the Two-Wire Serial Bus.
Theprescaler bits are zero or masked to zeroATmega8(L)2486O–AVR–10/04ATmega8(L)Slave Transmitter ModeIn the Slave Transmitter mode, a number of data bytes are transmitted to a MasterReceiver (see Figure 84). All the status codes mentioned in this section assume that theprescaler bits are zero or are masked to zero.Figure 84. Data Transfer in Slave Transmitter ModeVCCDevice 1Device 2SLAVETRANSMITTERMASTERRECEIVER........Device 3R1Device nR2SDASCLTo initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:TWARTWA6TWA5valueTWA4TWA3TWA2TWA1TWA0TWGCEDevice’s Own Slave AddressThe upper seven bits are the address to which the Two-wire Serial Interface will respondwhen addressed by a Master. If the LSB is set, the TWI will respond to the general calladdress (0x00), otherwise it will ignore the general call address.TWCRvalueTWINTTWEATWSTATWSTOTWWCTWEN–TWIE0100010XTWEN must be written to one to enable the TWI.
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