ATmega8 (961722), страница 40
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Optionally, AVCC or an internal 2.56V reference voltage may be connected to the AREF pin by writing to the REFSn bits in theADMUX Register. The internal voltage reference may thus be decoupled by an externalcapacitor at the AREF pin to improve noise immunity.The analog input channel is selected by writing to the MUX bits in ADMUX. Any of theADC input pins, as well as GND and a fixed bandgap voltage reference, can be selectedas single ended inputs to the ADC.
The ADC is enabled by setting the ADC Enable bit,ADEN in ADCSRA. Voltage reference and input channel selections will not go into effectuntil ADEN is set. The ADC does not consume power when ADEN is cleared, so it isrecommended to switch off the ADC before entering power saving sleep modes.The ADC generates a 10-bit result which is presented in the ADC Data Registers,ADCH and ADCL. By default, the result is presented right adjusted, but can optionallybe presented left adjusted by setting the ADLAR bit in ADMUX.194ATmega8(L)2486O–AVR–10/04ATmega8(L)If the result is left adjusted and no more than 8-bit precision is required, it is sufficient toread ADCH.
Otherwise, ADCL must be read first, then ADCH, to ensure that the contentof the Data Registers belongs to the same conversion. Once ADCL is read, ADC accessto Data Registers is blocked. This means that if ADCL has been read, and a conversioncompletes before ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Registers isre-enabled.The ADC has its own interrupt which can be triggered when a conversion completes.When ADC access to the Data Registers is prohibited between reading of ADCH andADCL, the interrupt will trigger even if the result is lost.Starting a ConversionA single conversion is started by writing a logical one to the ADC Start Conversion bit,ADSC. This bit stays high as long as the conversion is in progress and will be cleared byhardware when the conversion is completed.
If a different data channel is selected whilea conversion is in progress, the ADC will finish the current conversion before performingthe channel change.In Free Running mode, the ADC is constantly sampling and updating the ADC DataRegister. Free Running mode is selected by writing the ADFR bit in ADCSRA to one.The first conversion must be started by writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive conversions independently ofwhether the ADC Interrupt Flag, ADIF is cleared or not.Prescaling andConversion TimingFigure 91. ADC PrescalerADENSTARTReset7-BIT ADC PRESCALERCK/128CK/64CK/32CK/16CK/8CK/4CK/2CKADPS0ADPS1ADPS2ADC CLOCK SOURCEBy default, the successive approximation circuitry requires an input clock frequencybetween 50 kHz and 200 kHz to get maximum resolution.
If a lower resolution than 10bits is needed, the input clock frequency to the ADC can be higher than 200 kHz to get ahigher sample rate.The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bitsin ADCSRA. The prescaler starts counting from the moment the ADC is switched on bysetting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADENbit is set, and is continuously reset when ADEN is low.When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion starts at the following rising edge of the ADC clock cycle.
A normal conversion1952486O–AVR–10/04takes 13 ADC clock cycles. The first conversion after the ADC is switched on (ADEN inADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry.The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normalconversion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is complete, the result is written to the ADC Data Registers, and ADIF is set.
Insingle conversion mode, ADSC is cleared simultaneously. The software may then setADSC again, and a new conversion will be initiated on the first rising ADC clock edge.In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. For a summary of conversion times, seeTable 73.Figure 92. ADC Timing Diagram, First Conversion (Single Conversion Mode)NextConversionFirst ConversionCycle Number121213141516171819202122232425123ADC ClockADENADSCADIFADCHMSB of ResultADCLLSB of ResultMUX and REFSUpdateConversionCompleteSample & HoldMUX and REFSUpdateFigure 93. ADC Timing Diagram, Single ConversionOne ConversionCycle Number123456789Next Conversion10111213123ADC ClockADSCADIFADCHMSB of ResultADCLLSB of ResultSample & HoldMUX and REFSUpdate196ConversionCompleteMUX and REFSUpdateATmega8(L)2486O–AVR–10/04ATmega8(L)Figure 94.
ADC Timing Diagram, Free Running ConversionOne ConversionCycle Number1112Next Conversion131234ADC ClockADSCADIFADCHMSB of ResultADCLLSB of ResultSample &HoldConversionCompleteMUX and REFSUpdateTable 73. ADC Conversion TimeSample & Hold (Cyclesfrom Start of Conversion)Conversion Time(Cycles)Extended conversion13.525Normal conversions, single ended1.513ConditionChanging Channel orReference SelectionThe MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary register to which the CPU has random access. This ensures that the channelsand reference selection only takes place at a safe point during the conversion.
Thechannel and reference selection is continuously updated until a conversion is started.Once the conversion starts, the channel and reference selection is locked to ensure asufficient sampling time for the ADC. Continuous updating resumes in the last ADCclock cycle before the conversion completes (ADIF in ADCSRA is set). Note that theconversion starts on the following rising ADC clock edge after ADSC is written. The useris thus advised not to write new channel or reference selection values to ADMUX untilone ADC clock cycle after ADSC is written.If both ADFR and ADEN is written to one, an interrupt event can occur at any time.
If theADMUX Register is changed in this period, the user cannot tell if the next conversion isbased on the old or the new settings. ADMUX can be safely updated in the followingways:1. When ADFR or ADEN is cleared.2. During conversion, minimum one ADC clock cycle after the trigger event.3. After a conversion, before the Interrupt Flag used as trigger source is cleared.When updating ADMUX in one of these conditions, the new settings will affect the nextADC conversion.1972486O–AVR–10/04ADC Input ChannelsWhen changing channel selections, the user should observe the following guidelines toensure that the correct channel is selected:In Single Conversion mode, always select the channel before starting the conversion.The channel selection may be changed one ADC clock cycle after writing one to ADSC.However, the simplest method is to wait for the conversion to complete before changingthe channel selection.In Free Running mode, always select the channel before starting the first conversion.The channel selection may be changed one ADC clock cycle after writing one to ADSC.However, the simplest method is to wait for the first conversion to complete, and thenchange the channel selection.
Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversionswill reflect the new channel selection.ADC Voltage ReferenceThe reference voltage for the ADC (VREF) indicates the conversion range for the ADC.Single ended channels that exceed VREF will result in codes close to 0x3FF. VREF can beselected as either AVCC, internal 2.56V reference, or external AREF pin.AVCC is connected to the ADC through a passive switch. The internal 2.56V reference isgenerated from the internal bandgap reference (VBG) through an internal amplifier.
Ineither case, the external AREF pin is directly connected to the ADC, and the referencevoltage can be made more immune to noise by connecting a capacitor between theAREF pin and ground. VREF can also be measured at the AREF pin with a high impedantvoltmeter. Note that VREF is a high impedant source, and only a capacitive load shouldbe connected in a system.If the user has a fixed voltage source connected to the AREF pin, the user may not usethe other reference voltage options in the application, as they will be shorted to theexternal voltage. If no external voltage is applied to the AREF pin, the user may switchbetween AVCC and 2.56V as reference selection.
The first ADC conversion result afterswitching reference voltage source may be inaccurate, and the user is advised to discard this result.ADC Noise CancelerThe ADC features a noise canceler that enables conversion during sleep mode toreduce noise induced from the CPU core and other I/O peripherals. The noise cancelercan be used with ADC Noise Reduction and Idle mode. To make use of this feature, thefollowing procedure should be used:1. Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must be selected and the ADC conversion complete interruptmust be enabled.2. Enter ADC Noise Reduction mode (or Idle mode).
The ADC will start a conversion once the CPU has been halted.3. If no other interrupts occur before the ADC conversion completes, the ADCinterrupt will wake up the CPU and execute the ADC Conversion Completeinterrupt routine. If another interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be executed, and an ADC ConversionComplete interrupt request will be generated when the ADC conversioncompletes.
The CPU will remain in Active mode until a new sleep commandis executed.Note that the ADC will not be automatically turned off when entering other sleep modesthan Idle mode and ADC Noise Reduction mode. The user is advised to write zero toADEN before entering such sleep modes to avoid excessive power consumption.198ATmega8(L)2486O–AVR–10/04ATmega8(L)Analog Input CircuitryThe analog input circuitry for single ended channels is illustrated in Figure 95. An analogsource applied to ADCn is subjected to the pin capacitance and input leakage of thatpin, regardless of whether that channel is selected as input for the ADC.
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