ATmega8 (961722), страница 39
Текст из файла (страница 39)
In this case, arbitration will occur, either in the READ/WRITE bit or in the databits. The masters trying to output a one on SDA while another Master outputs a zerowill lose the arbitration. Losing masters will switch to not addressed Slave mode orwait until the bus is free and transmit a new START condition, depending onapplication software action.•Two or more masters are accessing different slaves. In this case, arbitration willoccur in the SLA bits. Masters trying to output a one on SDA while another Masteroutputs a zero will lose the arbitration. Masters losing arbitration in SLA will switch toSlave mode to check if they are being addressed by the winning Master. Ifaddressed, they will switch to SR or ST mode, depending on the value of theREAD/WRITE bit. If they are not being addressed, they will switch to not addressedSlave mode or wait until the bus is free and transmit a new START condition,depending on application software action.This is summarized in Figure 88.
Possible status values are given in circles.Figure 88. Possible Status Codes Caused by ArbitrationSTARTSLADataArbitration lost in SLAOwnAddress / General CallreceivedNoSTOPArbitration lost in Data38TWI bus will be released and not addressed slave mode will be enteredA START condition will be transmitted when the bus becomes freeYesDirectionWrite68/78ReadB0Data byte will be received and NOT ACK will be returnedData byte will be received and ACK will be returnedLast data byte will be transmitted and NOT ACK should be receivedData byte will be transmitted and ACK should be received1892486O–AVR–10/04Analog ComparatorThe Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1.
When the voltage on the positive pin AIN0 is higher than the voltage onthe negative pin AIN1, the Analog Comparator Output, ACO, is set. The comparator’soutput can be set to trigger the Timer/Counter1 Input Capture function. In addition, thecomparator can trigger a separate interrupt, exclusive to the Analog Comparator. Theuser can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 89.Figure 89.
Analog Comparator Block Diagram(2)BANDGAPREFERENCEACBGACMEADENADC MULTIPLEXEROUTPUT (1)Notes:Special Function IO Register –SFIOR1. See Table 72 on page 192.2. Refer to “Pin Configurations” on page 2 and Table 28 on page 61 for Analog Comparator pin placement.Bit76543210––––ACMEPUDPSR2PSR10Read/WriteRRRRR/WR/WR/WR/WInitial Value00000000SFIOR• Bit 3 – ACME: Analog Comparator Multiplexer EnableWhen this bit is written logic one and the ADC is switched off (ADEN in ADCSRA iszero), the ADC multiplexer selects the negative input to the Analog Comparator. Whenthis bit is written logic zero, AIN1 is applied to the negative input of the Analog Comparator.
For a detailed description of this bit, see “Analog Comparator Multiplexed Input” onpage 192.190ATmega8(L)2486O–AVR–10/04ATmega8(L)Analog Comparator Controland Status Register – ACSRBit76543210ACDACBGACOACIACIEACICACIS1ACIS0Read/WriteR/WR/WRR/WR/WR/WR/WR/WInitial Value00N/A00000ACSR• Bit 7 – ACD: Analog Comparator DisableWhen this bit is written logic one, the power to the Analog Comparator is switched off.This bit can be set at any time to turn off the Analog Comparator.
This will reduce powerconsumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interruptcan occur when the bit is changed.• Bit 6 – ACBG: Analog Comparator Bandgap SelectWhen this bit is set, a fixed bandgap reference voltage replaces the positive input to theAnalog Comparator. When this bit is cleared, AIN0 is applied to the positive input of theAnalog Comparator. See “Internal Voltage Reference” on page 40.• Bit 5 – ACO: Analog Comparator OutputThe output of the Analog Comparator is synchronized and then directly connected toACO.
The synchronization introduces a delay of 1 - 2 clock cycles.• Bit 4 – ACI: Analog Comparator Interrupt FlagThis bit is set by hardware when a comparator output event triggers the interrupt modedefined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed ifthe ACIE bit is set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, ACI is cleared by writinga logic one to the flag.• Bit 3 – ACIE: Analog Comparator Interrupt EnableWhen the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated.
When written logic zero, the interrupt is disabled.• Bit 2 – ACIC: Analog Comparator Input Capture EnableWhen written logic one, this bit enables the Input Capture function in Timer/Counter1 tobe triggered by the Analog Comparator. The comparator output is in this case directlyconnected to the Input Capture front-end logic, making the comparator utilize the noisecanceler and edge select features of the Timer/Counter1 Input Capture interrupt. Whenwritten logic zero, no connection between the Analog Comparator and the Input Capturefunction exists.
To make the comparator trigger the Timer/Counter1 Input Capture interrupt, the TICIE1 bit in the Timer Interrupt Mask Register (TIMSK) must be set.• Bits 1,0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode SelectThese bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 71.Table 71. ACIS1/ACIS0 SettingsACIS1ACIS0Interrupt Mode00Comparator Interrupt on Output Toggle01Reserved10Comparator Interrupt on Falling Output Edge11Comparator Interrupt on Rising Output Edge1912486O–AVR–10/04When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interruptcan occur when the bits are changed.Analog ComparatorMultiplexed InputIt is possible to select any of the ADC7..0(1) pins to replace the negative input to theAnalog Comparator. The ADC multiplexer is used to select this input, and consequentlythe ADC must be switched off to utilize this feature.
If the Analog Comparator Multiplexer Enable bit (ACME in SFIOR) is set and the ADC is switched off (ADEN inADCSRA is zero), MUX2..0 in ADMUX select the input pin to replace the negative inputto the Analog Comparator, as shown in Table 72. If ACME is cleared or ADEN is set,AIN1 is applied to the negative input to the Analog Comparator.Table 72. Analog Comparator Multiplexed Input(1)ACMEADENMUX2..00xxxxAIN111xxxAIN110000ADC010001ADC110010ADC210011ADC310100ADC410101ADC510110ADC610111ADC7Note:192Analog Comparator Negative Input1. ADC7..6 are only available in TQFP and MLF Package.ATmega8(L)2486O–AVR–10/04ATmega8(L)Analog-to-DigitalConverterFeatures•••••••••••••10-bit Resolution0.5 LSB Integral Non-linearity± 2 LSB Absolute Accuracy13 - 260 µs Conversion TimeUp to 15 kSPS at Maximum Resolution6 Multiplexed Single Ended Input Channels2 Additional Multiplexed Single Ended Input Channels (TQFP and MLF Package only)Optional Left Adjustment for ADC Result Readout0 - VCC ADC Input Voltage RangeSelectable 2.56V ADC Reference VoltageFree Running or Single Conversion ModeInterrupt on ADC Conversion CompleteSleep Mode Noise CancelerThe ATmega8 features a 10-bit successive approximation ADC.
The ADC is connectedto an 8-channel Analog Multiplexer which allows eight single-ended voltage inputs constructed from the pins of Port C. The single-ended voltage inputs refer to 0V (GND).The ADC contains a Sample and Hold circuit which ensures that the input voltage to theADC is held at a constant level during conversion. A block diagram of the ADC is shownin Figure 90.The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ morethan ± 0.3V from VCC.
See the paragraph “ADC Noise Canceler” on page 198 on how toconnect this pin.Internal reference voltages of nominally 2.56V or AVCC are provided On-chip. The voltage reference may be externally decoupled at the AREF pin by a capacitor for betternoise performance.1932486O–AVR–10/04Figure 90. Analog to Digital Converter Block Schematic OperationADC CONVERSIONCOMPLETE IRQ15ADC[9:0]ADPS1ADPS0ADPS2ADIFADFRADENADSC0ADC DATA REGISTER(ADCH/ADCL)ADC CTRL.
& STATUSREGISTER (ADCSRA)MUX0MUX2MUX1MUX3ADLARREFS0REFS1ADC MULTIPLEXERSELECT (ADMUX)ADIEADIF8-BIT DATA BUSMUX DECODERCHANNEL SELECTIONPRESCALERAVCCCONVERSION LOGICINTERNAL 2.56VREFERENCESAMPLE & HOLDCOMPARATORAREF10-BIT DAC+GNDBANDGAPREFERENCEADC7ADC6ADC5INPUTMUXADC MULTIPLEXEROUTPUTADC4ADC3ADC2ADC1ADC0The ADC converts an analog input voltage to a 10-bit digital value through successiveapproximation. The minimum value represents GND and the maximum value representsthe voltage on the AREF pin minus 1 LSB.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
