ATmega8 (961722), страница 41
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When the channel is selected, the source must drive the S/H capacitor through the series resistance(combined resistance in the input path).The ADC is optimized for analog signals with an output impedance of approximately10 kΩ or less. If such a source is used, the sampling time will be negligible. If a sourcewith higher impedance is used, the sampling time will depend on how long time thesource needs to charge the S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources with slowly varying signals, since thisminimizes the required charge transfer to the S/H capacitor.Signal components higher than the Nyquist frequency (fADC/2) should not be present foreither kind of channels, to avoid distortion from unpredictable signal convolution. Theuser is advised to remove high frequency components with a low-pass filter beforeapplying the signals as inputs to the ADC.Figure 95. Analog Input CircuitryIIHADCn1..100 kΩCS/H= 14 pFIILVCC/2Analog Noise CancelingTechniquesDigital circuitry inside and outside the device generates EMI which might affect theaccuracy of analog measurements.
If conversion accuracy is critical, the noise level canbe reduced by applying the following techniques:1. Keep analog signal paths as short as possible. Make sure analog tracks runover the ground plane, and keep them well away from high-speed switchingdigital tracks.2. The AVCC pin on the device should be connected to the digital VCC supplyvoltage via an LC network as shown in Figure 96.3. Use the ADC noise canceler function to reduce induced noise from the CPU.4. If any ADC [3..0] port pins are used as digital outputs, it is essential thatthese do not switch while a conversion is in progress. However, using theTwo-wire Interface (ADC4 and ADC5) will only affect the conversion onADC4 and ADC5 and not the other ADC channels.1992486O–AVR–10/04Analog Ground PlanePC2 (ADC2)PC3 (ADC3)PC4 (ADC4/SDA)PC5 (ADC5/SCL)VCCGNDFigure 96. ADC Power ConnectionsPC1 (ADC1)PC0 (ADC0)ADC710µHGNDAREF100nFADC6AVCCPB5ADC Accuracy DefinitionsAn n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2nsteps (LSBs).
The lowest code is read as 0, and the highest code is read as 2n-1.Several parameters describe the deviation from the ideal behavior:•Offset: The deviation of the first transition (0x000 to 0x001) compared to the idealtransition (at 0.5 LSB). Ideal value: 0 LSB.Figure 97. Offset ErrorOutput CodeIdeal ADCActual ADCOffsetError200VREF Input VoltageATmega8(L)2486O–AVR–10/04ATmega8(L)•Gain error: After adjusting for offset, the gain error is found as the deviation of thelast transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB belowmaximum).
Ideal value: 0 LSBFigure 98. Gain ErrorGainErrorOutput CodeIdeal ADCActual ADCVREF Input Voltage•Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is themaximum deviation of an actual transition compared to an ideal transition for anycode. Ideal value: 0 LSB.Figure 99. Integral Non-linearity (INL)Output CodeINLIdeal ADCActual ADCVREF•Input VoltageDifferential Non-linearity (DNL): The maximum deviation of the actual code width(the interval between two adjacent transitions) from the ideal code width (1 LSB).Ideal value: 0 LSB.2012486O–AVR–10/04Figure 100. Differential Non-linearity (DNL)Output Code0x3FF1 LSBDNL0x0000ADC Conversion ResultVREF Input Voltage•Quantization Error: Due to the quantization of the input voltage into a finite numberof codes, a range of input voltages (1 LSB wide) will code to the same value.
Always±0.5 LSB.•Absolute accuracy: The maximum deviation of an actual (unadjusted) transitioncompared to an ideal transition for any code. This is the compound effect of offset,gain error, differential error, non-linearity, and quantization error.
Ideal value: ±0.5LSB.After the conversion is complete (ADIF is high), the conversion result can be found inthe ADC Result Registers (ADCL, ADCH).For single ended conversion, the result isV IN ⋅ 1024ADC = -------------------------V REFwhere VIN is the voltage on the selected input pin and VREF the selected voltage reference (see Table 74 on page 203 and Table 75 on page 203). 0x000 represents ground,and 0x3FF represents the selected reference voltage minus one LSB.ADC Multiplexer SelectionRegister – ADMUXBit76543210REFS1REFS0ADLAR–MUX3MUX2MUX1MUX0Read/WriteR/WR/WR/WRR/WR/WR/WR/WInitial Value00000000ADMUX• Bit 7:6 – REFS1:0: Reference Selection BitsThese bits select the voltage reference for the ADC, as shown in Table 74.
If these bitsare changed during a conversion, the change will not go in effect until this conversion iscomplete (ADIF in ADCSRA is set). The internal voltage reference options may not beused if an external reference voltage is being applied to the AREF pin.202ATmega8(L)2486O–AVR–10/04ATmega8(L)Table 74. Voltage Reference Selections for ADC•REFS1REFS0Voltage Reference Selection00AREF, Internal Vref turned off01AVCC with external capacitor at AREF pin10Reserved11Internal 2.56V Voltage Reference with external capacitor at AREF pinBit 5 – ADLAR: ADC Left Adjust ResultThe ADLAR bit affects the presentation of the ADC conversion result in the ADC DataRegister. Write one to ADLAR to left adjust the result.
Otherwise, the result is rightadjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,regardless of any ongoing conversions. For a complete description of this bit, see “TheADC Data Register – ADCL and ADCH” on page 205.• Bits 3:0 – MUX3:0: Analog Channel Selection BitsThe value of these bits selects which analog inputs are connected to the ADC. SeeTable 75 for details. If these bits are changed during a conversion, the change will notgo in effect until this conversion is complete (ADIF in ADCSRA is set).Table 75. Input Channel SelectionsMUX3..0Single Ended Input0000ADC00001ADC10010ADC20011ADC30100ADC40101ADC50110ADC60111ADC710001001101010111100110111101.23V (VBG)11110V (GND)2032486O–AVR–10/04ADC Control and StatusRegister A – ADCSRABit76543210ADENADSCADFRADIFADIEADPS2ADPS1ADPS0Read/WriteR/WR/WR/WR/WR/WR/WR/WR/WInitial Value00000000ADCSRA• Bit 7 – ADEN: ADC EnableWriting this bit to one enables the ADC.
By writing it to zero, the ADC is turned off. Turning the ADC off while a conversion is in progress, will terminate this conversion.• Bit 6 – ADSC: ADC Start ConversionIn Single Conversion mode, write this bit to one to start each conversion. In Free Running mode, write this bit to one to start the first conversion. The first conversion afterADSC has been written after the ADC has been enabled, or if ADSC is written at thesame time as the ADC is enabled, will take 25 ADC clock cycles instead of the normal13. This first conversion performs initialization of the ADC.ADSC will read as one as long as a conversion is in progress. When the conversion iscomplete, it returns to zero.
Writing zero to this bit has no effect.• Bit 5 – ADFR: ADC Free Running SelectWhen this bit is set (one) the ADC operates in Free Running mode. In this mode, theADC samples and updates the Data Registers continuously. Clearing this bit (zero) willterminate Free Running mode.• Bit 4 – ADIF: ADC Interrupt FlagThis bit is set when an ADC conversion completes and the Data Registers are updated.The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit inSREG are set. ADIF is cleared by hardware when executing the corresponding interruptHandling Vector. Alternatively, ADIF is cleared by writing a logical one to the flag.Beware that if doing a Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions are used.• Bit 3 – ADIE: ADC Interrupt EnableWhen this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated.204ATmega8(L)2486O–AVR–10/04ATmega8(L)• Bits 2:0 – ADPS2:0: ADC Prescaler Select BitsThese bits determine the division factor between the XTAL frequency and the inputclock to the ADC.Table 76.
ADC Prescaler SelectionsADPS2ADPS1ADPS0Division Factor0002001201040118100161013211064111128The ADC Data Register – ADCL and ADCHADLAR = 0BitRead/WriteInitial Value15141312111098––––––ADC9ADC8ADCHADC7ADC6ADC5ADC4ADC3ADC2ADC1ADC0ADCL76543210RRRRRRRRRRRRRRRR0000000000000000ADLAR = 1BitRead/WriteInitial Value15141312111098ADC9ADC8ADC7ADC6ADC5ADC4ADC3ADC2ADCHADC1ADC0––––––ADCL76543210RRRRRRRRRRRRRRRR0000000000000000When an ADC conversion is complete, the result is found in these two registers.When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it issufficient to read ADCH.
Otherwise, ADCL must be read first, then ADCH.The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result isread from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared(default), the result is right adjusted.• ADC9:0: ADC Conversion resultThese bits represent the result from the conversion, as detailed in “ADC ConversionResult” on page 202.2052486O–AVR–10/04Boot Loader Support– Read-While-WriteSelf-ProgrammingThe Boot Loader Support provides a real Read-While-Write Self-Programming mechanism for downloading and uploading program code by the MCU itself.
This featureallows flexible application software updates controlled by the MCU using a Flash-resident Boot Loader program. The Boot Loader program can use any available datainterface and associated protocol to read code and write (program) that code into theFlash memory, or read the code from the Program memory. The program code withinthe Boot Loader section has the capability to write into the entire Flash, including theBoot Loader Memory. The Boot Loader can thus even modify itself, and it can alsoerase itself from the code if the feature is not needed anymore.
The size of the BootLoader Memory is configurable with fuses and the Boot Loader has two separate sets ofBoot Lock Bits which can be set independently. This gives the user a unique flexibility toselect different levels of protection.Boot Loader Features•••••••Read-While-Write Self-ProgrammingFlexible Boot Memory SizeHigh Security (Separate Boot Lock Bits for a Flexible Protection)Separate Fuse to Select Reset VectorOptimized Page(1) SizeCode Efficient AlgorithmEfficient Read-Modify-Write SupportNote:1. A page is a section in the Flash consisting of several bytes (see Table 89 on page222) used during programming. The page organization does not affect normaloperation.Application and BootLoader Flash SectionsThe Flash memory is organized in two main sections, the Application section and theBoot loader section (see Figure 102).
The size of the different sections is configured bythe BOOTSZ Fuses as shown in Table 82 on page 217 and Figure 102. These two sections can have different level of protection since they have different sets of Lock Bits.Application SectionThe application section is the section of the Flash that is used for storing the applicationcode. The protection level for the application section can be selected by the applicationboot Lock Bits (Boot Lock Bits 0), see Table 78 on page 209.
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