ATmega8 (961722), страница 32

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UCSZ Bits SettingsUCSZ2UCSZ1UCSZ0Character Size0005-bit0016-bit0107-bit0118-bit100Reserved101Reserved110Reserved1119-bit• Bit 0 – UCPOL: Clock Polarity154ATmega8(L)2486O–AVR–10/04ATmega8(L)This bit is used for Synchronous mode only. Write this bit to zero when Asynchronousmode is used. The UCPOL bit sets the relationship between data output change anddata input sample, and the synchronous clock (XCK).Table 59. UCPOL Bit SettingsTransmitted Data Changed (Output ofTxD Pin)Received Data Sampled (Input onRxD Pin)0Rising XCK EdgeFalling XCK Edge1Falling XCK EdgeRising XCK EdgeUCPOLUSART Baud Rate Registers –UBRRL and UBRRHsBit15141312URSEL–––111098UBRR[11:8]UBRRHUBRR[7:0]7Read/WriteInitial Value65UBRRL43210R/WRRRR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/W0000000000000000The UBRRH Register shares the same I/O location as the UCSRC Register.

See the“Accessing UBRRH/UCSRC Registers” on page 149 section which describes how toaccess this register.• Bit 15 – URSEL: Register SelectThis bit selects between accessing the UBRRH or the UCSRC Register. It is read aszero when reading UBRRH.

The URSEL must be zero when writing the UBRRH.• Bit 14:12 – Reserved BitsThese bits are reserved for future use. For compatibility with future devices, these bitmust be written to zero when UBRRH is written.• Bit 11:0 – UBRR11:0: USART Baud Rate RegisterThis is a 12-bit register which contains the USART baud rate. The UBRRH contains thefour most significant bits, and the UBRRL contains the eight least significant bits of theUSART baud rate. Ongoing transmissions by the Transmitter and Receiver will be corrupted if the baud rate is changed.

Writing UBRRL will trigger an immediate update ofthe baud rate prescaler.1552486O–AVR–10/04Examples of Baud RateSettingFor standard crystal and resonator frequencies, the most commonly used baud rates forasynchronous operation can be generated by using the UBRR settings in Table 60.UBRR values which yield an actual baud rate differing less than 0.5% from the targetbaud rate, are bold in the table. Higher error ratings are acceptable, but the Receiver willhave less noise resistance when the error ratings are high, especially for large serialframes (see “Asynchronous Operational Range” on page 146). The error values are calculated using the following equation:BaudRate Closest Match- – 1⎞⎠ • 100%Error[%] = ⎛⎝ ------------------------------------------------------BaudRateTable 60. Examples of UBRR Settings for Commonly Used Oscillator Frequenciesfosc = 1.0000 MHzfosc = 1.8432 MHzfosc = 2.0000 MHzBaudRate(bps)UBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRError2400250.2%510.2%470.0%950.0%510.2%1030.2%4800120.2%250.2%230.0%470.0%250.2%510.2%96006-7.0%120.2%110.0%230.0%120.2%250.2%14.4k38.5%8-3.5%70.0%150.0%8-3.5%162.1%19.2k28.5%6-7.0%50.0%110.0%6-7.0%120.2%28.8k18.5%38.5%30.0%70.0%38.5%8-3.5%38.4k1-18.6%28.5%20.0%50.0%28.5%6-7.0%57.6k08.5%18.5%10.0%30.0%18.5%38.5%76.8k––1-18.6%1-25.0%20.0%1-18.6%28.5%115.2k––08.5%00.0%10.0%08.5%18.5%230.4k––––––00.0%–-––250k––––––––––00.0%Max1.156(1)U2X = 0U2X = 162.5 kbps125 kbpsU2X = 0U2X = 1115.2 kbpsU2X = 0230.4 kbps125 kbpsU2X = 1250 kbpsUBRR = 0, Error = 0.0%ATmega8(L)2486O–AVR–10/04ATmega8(L)Table 61.

Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)fosc = 3.6864 MHzfosc = 4.0000 MHzfosc = 7.3728 MHzBaudRate(bps)UBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRError2400950.0%1910.0%1030.2%2070.2%1910.0%3830.0%4800470.0%950.0%510.2%1030.2%950.0%1910.0%9600230.0%470.0%250.2%510.2%470.0%950.0%14.4k150.0%310.0%162.1%34-0.8%310.0%630.0%19.2k110.0%230.0%120.2%250.2%230.0%470.0%28.8k70.0%150.0%8-3.5%162.1%150.0%310.0%38.4k50.0%110.0%6-7.0%120.2%110.0%230.0%57.6k30.0%70.0%38.5%8-3.5%70.0%150.0%76.8k20.0%50.0%28.5%6-7.0%50.0%110.0%115.2k10.0%30.0%18.5%38.5%30.0%70.0%230.4k00.0%10.0%08.5%18.5%10.0%30.0%250k0-7.8%1-7.8%00.0%10.0%1-7.8%3-7.8%0.5M––0-7.8%––00.0%0-7.8%1-7.8%1M––––––––––0-7.8%Max1.U2X = 0(1)U2X = 1230.4 kbpsU2X = 0460.8 kbps250 kbpsU2X = 1U2X = 00.5 MbpsU2X = 1460.8 kbps921.6 kbpsUBRR = 0, Error = 0.0%1572486O–AVR–10/04Table 62. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)fosc = 11.0592 MHzfosc = 8.0000 MHzfosc = 14.7456 MHzBaudRate(bps)UBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRError24002070.2%416-0.1%2870.0%5750.0%3830.0%7670.0%48001030.2%2070.2%1430.0%2870.0%1910.0%3830.0%9600510.2%1030.2%710.0%1430.0%950.0%1910.0%14.4k34-0.8%680.6%470.0%950.0%630.0%1270.0%19.2k250.2%510.2%350.0%710.0%470.0%950.0%28.8k162.1%34-0.8%230.0%470.0%310.0%630.0%38.4k120.2%250.2%170.0%350.0%230.0%470.0%57.6k8-3.5%162.1%110.0%230.0%150.0%310.0%76.8k6-7.0%120.2%80.0%170.0%110.0%230.0%115.2k38.5%8-3.5%50.0%110.0%70.0%150.0%230.4k18.5%38.5%20.0%50.0%30.0%70.0%250k10.0%30.0%2-7.8%5-7.8%3-7.8%65.3%0.5M00.0%10.0%––2-7.8%1-7.8%3-7.8%1M––00.0%––––0-7.8%1-7.8%Max1.158(1)U2X = 00.5 MbpsU2X = 11 MbpsU2X = 0691.2 kbpsU2X = 11.3824 MbpsU2X = 0921.6 kbpsU2X = 11.8432 MbpsUBRR = 0, Error = 0.0%ATmega8(L)2486O–AVR–10/04ATmega8(L)Table 63.

Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)fosc = 16.0000 MHzfosc = 18.4320 MHzfosc = 20.0000 MHzBaudRate(bps)UBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRErrorUBRRError2400416-0.1%8320.0%4790.0%9590.0%5200.0%10410.0%48002070.2%416-0.1%2390.0%4790.0%2590.2%5200.0%96001030.2%2070.2%1190.0%2390.0%1290.2%2590.2%14.4k680.6%138-0.1%790.0%1590.0%86-0.2%173-0.2%19.2k510.2%1030.2%590.0%1190.0%640.2%1290.2%28.8k34-0.8%680.6%390.0%790.0%420.9%86-0.2%38.4k250.2%510.2%290.0%590.0%32-1.4%640.2%57.6k162.1%34-0.8%190.0%390.0%21-1.4%420.9%76.8k120.2%250.2%140.0%290.0%151.7%32-1.4%115.2k8-3.5%162.1%90.0%190.0%10-1.4%21-1.4%230.4k38.5%8-3.5%40.0%90.0%48.5%10-1.4%250k30.0%70.0%4-7.8%82.4%40.0%90.0%0.5M10.0%30.0%––4-7.8%––40.0%1M00.0%10.0%––––––––Max1.U2X = 0(1)1 MbpsU2X = 12 MbpsU2X = 0U2X = 11.152 MbpsU2X = 02.304 MbpsU2X = 11.25 Mbps2.5 MbpsUBRR = 0, Error = 0.0%1592486O–AVR–10/04Two-wire SerialInterfaceFeatures••••••••••Two-wire Serial InterfaceBus DefinitionThe Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications.

The TWI protocol allows the systems designer to interconnect up to 128 differentdevices using only two bi-directional bus lines, one for clock (SCL) and one for data(SDA). The only external hardware needed to implement the bus is a single pull-upresistor for each of the TWI bus lines. All devices connected to the bus have individualaddresses, and mechanisms for resolving bus contention are inherent in the TWIprotocol.Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines NeededBoth Master and Slave Operation SupportedDevice can Operate as Transmitter or Receiver7-bit Address Space Allows up to 128 Different Slave AddressesMulti-master Arbitration SupportUp to 400 kHz Data Transfer SpeedSlew-rate Limited Output DriversNoise Suppression Circuitry Rejects Spikes on Bus LinesFully Programmable Slave Address with General Call SupportAddress Recognition Causes Wake-up When AVR is in Sleep ModeFigure 68.

TWI Bus InterconnectionVCCDevice 1Device 2Device 3........Device nR1R2SDASCLTWI TerminologyThe following definitions are frequently encountered in this section.Table 64. TWI Terminology160TermDescriptionMasterThe device that initiates and terminates a transmission. The Master alsogenerates the SCL clock.SlaveThe device addressed by a Master.TransmitterThe device placing data on the bus.ReceiverThe device reading data from the bus.ATmega8(L)2486O–AVR–10/04ATmega8(L)Electrical InterconnectionAs depicted in Figure 68, both bus lines are connected to the positive supply voltagethrough pull-up resistors.

The bus drivers of all TWI-compliant devices are open-drain oropen-collector. This implements a wired-AND function which is essential to the operation of the interface. A low level on a TWI bus line is generated when one or more TWIdevices output a zero. A high level is output when all TWI devices tri-state their outputs,allowing the pull-up resistors to pull the line high. Note that all AVR devices connected tothe TWI bus must be powered in order to allow any bus operation.The number of devices that can be connected to the bus is only limited by the buscapacitance limit of 400 pF and the 7-bit slave address space.

A detailed specification ofthe electrical characteristics of the TWI is given in “Two-wire Serial Interface Characteristics” on page 242. Two different sets of specifications are presented there, onerelevant for bus speeds below 100 kHz, and one valid for bus speeds up to 400 kHz.Data Transfer and FrameFormatTransferring BitsEach data bit transferred on the TWI bus is accompanied by a pulse on the clock line.The level of the data line must be stable when the clock line is high.

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