Volume 1 Application Programming (794095), страница 73
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The destination and thedestinationTOP are not changed.Note:1. For all unmasked exceptions, the processor’s response also includes assertion of the FERR# output signal at thecompletion of the instruction that caused the exception.2. When CR0.NE is set to 1, the #MF service routine is taken at the next non-control x87 instruction. If CR0.NE iscleared to zero, x87 floating-point instructions are handled by setting the FERR# input signal to 1, which externallogic can use to handle the interrupt.FERR# and IGNNE# Signals. In all unmasked-exception responses, the processor also asserts theFERR# output signal at the completion of the instruction that caused the exception. The exception isserviced at the boundary of the next non-waiting x87 or 64-bit media instruction following theinstruction that caused the exception.
(See “Control” on page 274 for a definition of controlinstructions.)System software controls x87 floating-point exception reporting using the numeric error (NE) bit incontrol register 0 (CR0), as follows:•If CR0.NE = 1, internal processor control over x87 floating-point exception reporting is enabled.In this case, an #MF exception occurs immediately. The FERR# output signal is asserted, but is not290x87 Floating-Point Programming24592—Rev. 3.13—July 2007•AMD64 Technologyused externally.
It is recommended that system software set NE to 1. This enables optimalperformance in handling x87 floating-point exceptions.If CR0.NE = 0, internal processor control of x87 floating-point exceptions is disabled and theexternal IGNNE# input signal controls whether x87 floating-point exceptions are ignored, asfollows:- When IGNNE# is 0, x87 floating-point exceptions are reported by asserting the FERR# outputsignal, then stopping program execution until an external interrupt is detected.
External logicuse the FERR# signal to generate the external interrupt.- When IGNNE# is 1, x87 floating-point exceptions do not stop program execution. AfterFERR# is asserted, instructions continue to execute.Using NaNs in IE Diagnostic Exceptions. Both SNaNs and QNaNs can be encoded with manydifferent values to carry diagnostic information. By means of appropriate masking and unmasking ofthe invalid-operation exception (IE), software can use signaling NaNs to invoke an exception handler.Within the constraints imposed by the encoding of SNaNs and QNaNs, software may freely assign thebits in the significand of a NaN. See the section “Not a Number (NaN)” on page 256 for format details.For example, software can pre-load each element of an array with a signaling NaN that encodes thearray index. When an application accesses an uninitialized array element, the invalid-operationexception is invoked and the service routine can identify that element.
A service routine can storedebug information in memory as the exceptions occur. The routine can create a QNaN that referencesits associated debug area in memory. As the program runs, the service routine can create a differentQNaN for each error condition, so that a single test-run can identify a collection of errors.6.9State-SavingIn general, system software should save and restore x87 state between task switches or otherinterventions in the execution of x87 floating-point procedures. Virtually all modern operating systemsrunning on x86 processors—like Windows NT®, UNIX, and OS/2—are preemptive multitaskingoperating systems that handle such saving and restoring of state properly across task switches,independently of hardware task-switch support.
However, application procedures are also free to saveand restore x87 state at any time they deem useful.6.9.1 State-Saving InstructionsFSAVE/FNSAVE and FRSTOR Instructions. Application software can save and restore the x87state by executing the FSAVE (or FNSAVE) and FRSTOR instructions. Alternatively, software mayuse multiple FxSTx (floating-point store stack top) instructions for saving only the contents of the x87data registers, rather than the complete x87 state.The FSAVE instruction stores the state, but only after handling any pending unmasked x87 floatingpoint exceptions, whereas the FNSAVE instruction skips the handling of these exceptions.
The state ofall x87 data registers is saved, as well as all x87 environment state (the x87 control word register, statusx87 Floating-Point Programming291AMD64 Technology24592—Rev. 3.13—July 2007word register, tag word, instruction pointer, data pointer, and last opcode register). After saving thisstate, the tag bits for all x87 registers are changed to empty and thus available for a new procedure.FXSAVE and FXRSTOR Instructions. Application software can save and restore the 128-bit mediastate, 64-bit media state, and x87 floating-point state by executing the FXSAVE and FXRSTORinstructions. The FXSAVE and FXRSTOR instructions execute faster than FSAVE/FNSAVE andFRSTOR because they do not save and restore the x87 pointers (last instruction pointer, last datapointer, and last opcode, described in “Pointers and Opcode State” on page 247) except in therelatively rare cases in which the exception-summary (ES) bit in the x87 status word (the ES registerimage for FXSAVE, or the ES memory image for FXRSTOR) is set to 1, indicating that an unmaskedx87 exception has occurred.Unlike FSAVE and FNSAVE, however, FXSAVE does not alter the tag bits.
The state of the saved x87data registers is retained, thus indicating that the registers may still be valid (or whatever other valuethe tag bits indicated prior to the save). To invalidate the contents of the x87 data registers afterFXSAVE, software must explicitly execute an FINIT instruction. Also, FXSAVE (like FNSAVE) andFXRSTOR do not check for pending unmasked x87 floating-point exceptions. An FWAIT instructioncan be used for this purpose.The architecture supports two memory formats for FXSAVE and FXRSTOR, a 512-byte 32-bit legacyformat and a 512-byte 64-bit format, used in 64-bit mode. Selection of the 32-bit or 64-bit format isdetermined by the effective operand size for the FXSAVE and FXRSTOR instructions.
For details, see“Media and x87 Processor State” in Volume 2.6.10Performance ConsiderationsIn addition to typical code optimization techniques, such as those affecting loops and the inlining offunction calls, the following considerations may help improve the performance of applicationprograms written with x87 floating-point instructions.These are implementation-independent performance considerations.
Other considerations depend onthe hardware implementation. For information about such implementation-dependent considerationsand for more information about application performance in general, see the data sheets and thesoftware-optimization guides relating to particular hardware implementations.6.10.1 Replace x87 Code with 128-Bit Media CodeCode written with 128-bit media floating-point instructions can operate in parallel on four times asmany single-precision floating-point operands as can x87 floating-point code. This achievespotentially four times the computational work of x87 instructions that use single-precision operands.Also, the higher density of 128-bit media floating-point operands may make it possible to remove localtemporary variables that would otherwise be needed in x87 floating-point code.
128-bit media code iseasier to write than x87 floating-point code, because the XMM register file is flat rather than stackoriented, and, in 64-bit mode there are twice the number of XMM registers as x87 registers.292x87 Floating-Point Programming24592—Rev. 3.13—July 2007AMD64 Technology6.10.2 Use FCOMI-FCMOVx BranchingDepending on the hardware implementation of the architecture, the combination of FCOMI andFCMOVcc is often faster than the classical approach using FxSTSW AX instructions for comparisonbased branches that depend on the condition codes for branch direction, because FNSTSW AX is oftena serializing instruction.6.10.3 Use FSINCOS Instead of FSIN and FCOSFrequently, a piece of code that needs to compute the sine of an argument also needs to compute thecosine of that same argument.
In such cases, use the FSINCOS instruction to compute bothtrigonometric functions concurrently, which is faster than using separate FSIN and FCOS instructionsto accomplish the same task.6.10.4 Break Up Dependency ChainsParallelism can be increased by breaking up dependency chains or by evaluating multiple dependencychains simultaneously (explicitly switching execution between them). Depending on the hardwareimplementation of the architecture, the FXCH instruction may prove faster than FST/FLD pairs forswitching execution between dependency chains.x87 Floating-Point Programming293AMD64 Technology29424592—Rev.
3.13—July 2007x87 Floating-Point Programming24592—Rev. 3.13—July 2007AMD64 TechnologyIndexSymbols#AC exception ......................................................... 88#BP exception ......................................................... 87#BR exception ......................................................... 87#DB exception ......................................................... 87#DE exception .........................................................
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