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This pin count effect is contained in the parameter N inequations 6, 7, and 8. On the other hand, the relative area penalty is much greater at lower pin counts. This effect isfortuitous, since an increasing number of ASIC designs in the pin count range well above 208 are pad-limited. Thehigher-pin-count designs have a significantly higher average selling price and thus provide the greatest potential for costreduction.
Such designs are currently packaged in expensive double-tiered ceramic packages. In addition to the costreduction resulting from the reduced die size, radial staggering technology provides the interesting additional potential forreducing the cost of the package itself by making it possible to design the ICs into cheaper packages based on a single layerof dense routing as opposed to multitiered structures. This can be achieved by the iterative coupled design procedurealluded to briefly in the foregoing section.2Reduction of Wire SweepWhile radial staggering helps reduce the effective I/O pad pitch and therefore the die size, the length of wires increasesproportionately, thus accentuating the wire sweep phenomenon.
Table I illustrates typical wire lengths that result fromreduction of die pad pitch. As a reference point, today’s state of the art for transfer molding technology permits wires nolonger than 4.5 mm (0.177 inch) to ensure 6s manufacturing quality levels.Table IWire Lengths for Different Die Pad Pitchesand Leadframe DesignsEffectiveDie PadPitch (mm)Longest Wire withConventional Leadframe (mm (inch))Longest Wire with NewLeadframe Design(mm (inch))0.1104.3 (0.170)3.8 (0.150)0.0905.1 (0.200)4.4 (0.173)0.0705.5 (0.216)4.9 (0.193)0.0506.0 (0.236)5.5 (0.216)The dual-looping scheme (Fig.
12) was developed to mitigate wire sweep. In this scheme, wire trajectories are placed in twodifferent planes rather than in the same plane, thus creating a vertical gap in addition to the x-y separation between any twoconsecutive bond wires. Since wire displacements resulting from sweep typically occur within the same plane, the requireddisplacement of a wire to cause shorting with an adjacent wire is effectively doubled compared to the case without duallooping, thereby considerably reducing the propensity for electrical shorts or leakage.The separation distance between the two planes in Fig.
12 is nominally 0.125 mm (0.005 inch). Such a design is madepossible by virtue of the loop height control features provided by state-of-the-art wire bonders. Loop heights are controllableto within "0.025 mm (0.001 inch) of the nominal value. Typically, the loop height for the outer row of bond pads is chosen tobe lower, and the outer row of pads is bonded first, followed by the inner row, to ensure that there is no interferencebetween the capillary and the loop portion of the previously bonded wire. Since the loop heights and bonding sequence areprogrammable, the entire bonding operation can be performed in automatic mode without compromising the processthroughput.
The nominal loop heights used in this work were 0.400 mm (0.016 inch) for the inner row of pads and 0.275 mm(0.011 inch) for the outer row of pads.Article 6December 1996 Hewlett-Packard Journal8Fig. 12. An SEM micrograph illustrating the dual-loop wire bonding scheme.New Leadframe DesignAs is evident from Table I, a reduction of effective pitch to 0.090 mm would lead to a longest wire of approximately 5.1 mm(0.200 inch) if a leadframe with conventional design were used. We have developed a new leadframe design that has reducedthe longest wire to 4.4 mm (0.173 inch), which was crucial in reducing wire sweep.Conventional leadframes are designed using standard CAD tools that have built-in algorithms for bond finger layout.
Bystudying the existing CAD tools, we learned that such tools likely employ a minimization of approach angles algorithm inconjunction with technology limit parameters (such as minimum bond finger width and space) to perform the layout ofbonding fingers for the leadframe. The technology limit parameters are derived from the design rules supplied by theleadframe manufacturers. For example, typical design rules for leadframes produced by etching technology are 0.1 mmwidth and 0.1 mm space, and for leadframes made using stamping technology, they are 0.125 mm width and 0.125 mm space.We observed that, from a mathematical standpoint, the minimization of wire lengths and the minimization of approachangles (in conjunction with the minimum width and space constraints) can be mutually conflicting conditions. This point isillustrated in Fig.
13. In Fig. 13a, the angles of approach have been minimized (they are zero degrees for all of the bondwires), whereas in Fig. 13b, the wire lengths have been minimized, but the approach angles are nonzero, and are as high as30 degrees for some wires. While the design in Fig. 13b has appreciably shorter wires, it is unfeasible to manufacturebecause it violates the specification for the maximum angle of approach of 10 degrees.After pursuing a theoretical analysis, we arrived at a straightforward (perhaps excruciatingly simple!) graphical methodfor the layout of bond fingers that would minimize the length of bond wires. The basis for this method is the theoreticalcondition that the bond fingers can be brought in closest to the center when the minimum widths and spaces reach thedesign rule limit values simultaneously at the tips of all bond fingers.
It can be shown that this condition is attained by layingout the bond fingers so that they subtend equal angles with respect to a convergence point.2 This latter fact formed the basisfor a simple graphical method for performing the bond finger layout. Based on this simple algorithm, a leadframe layout wasperformed for a 208-pin device and a bonding diagram was generated for a presumed die with radially staggered bond padsat 0.090-mm effective pitch (e.g., see Fig. 5).
The approach angles were calculated for this case, and the maximum value wasfound to be seven degrees, well below the manufacturing specification of 10 degrees. More important, the longest wire couldbe reduced to 4.4 mm (0.173 inch) compared to approximately 5.1 mm (0.200 inch) for a conventional leadframe.While the methodology has been illustrated for leadframes, it is more generally applicable to the design of other packagesubstrates, notably high-performance ball-grid arrays. The technology limit design rules for these substrates are moreaggressive (e.g., 0.05 mm width and 0.05 mm space), but significantly shorter wires are required to minimize parasiticinductance. In the above analysis, the minimization of wire length algorithm was used in place of the minimization of angleof approach algorithm, and the resulting angles of approach (verified afterwards) fortuitously fell within the 10-degree limit.This fortuitous condition does not always occur, especially in the regime of very short wire lengths and double-tieredpackage structures.
Therefore, a systematic iterative procedure is required that judiciously employs both algorithms andinvolves a coupled design of the radially staggered layout on the die and the bond finger layout on the package.2Article 6December 1996 Hewlett-Packard Journal9Bond Fingers of LeadframeBond Fingers of LeadframeWiresWires(a)Radially Staggered Bond Pads on a Die(b)Radially Staggered Bond Pads on a DieFig. 13. Role of leadframe design in angle of approach and wire length reduction.
(a) The anglesof approach have been minimized. (b) The wire lengths have been minimized. In both cases, theleadframe design rules (minimum width and spacing of leads) are the same.Assembly EvaluationsThe three key elements of the fine-pitch bonding solution described above are radially staggered bond pads, dual-loopbonding, and a new leadframe design. Extensive assembly and testing were performed to establish the feasibility of theseelements.
A 208-pin plastic package was used as the test vehicle.A test chip with 208 pads (N 208) and having a radially staggered pad configuration was designed and fabricated. Thephysical structure conformed to standard design rules for the current generation of the CMOS process at HP’s Corvallisfacility. The effective pitch, p, was 0.0889 mm, the offset distance between the inner and outer row of pads, d, was 0.140 mm,and the pad height, H, was 0.660 mm. Since N/4 is even, equations 3 and 4 were applied with a value of c 0.110 mm, basedon the lowest inline pitch capability available at the time. Using the parameters above, the die size worked out to be 6.02mm.
Details of the chip layout can be found in the Article 7.Daisy chains were incorporated in the design to check for leakage current between adjacent bond pads. This feature wasmotivated by the need to test the susceptibility to wire sweep, which is known to manifest itself as an electrical leakagebetween adjacent bond wires (the leakage at every bond wire can be monitored externally using the package pins).In addition, a 208-pin leadframe was designed and fabricated by the etching method using the principle of minimization ofwire length. The leadframe was fabricated by an external leadframe supplier using standard design rules and productionmethods.Assembly and Test ResultsThe die was assembled in a 208-pin PQFP package at HP’s production facility in Singapore.
A dual-loop bonding process wasdeveloped and the dual looping was performed in automatic mode on production wire bonders. A simple electrical testprogram was used to perform package testing on a production tester to check for open bonds (continuity) and electricalleakage between adjacent pins. In addition, transmission X-ray analysis was done on finished packages to check for physicalevidence of wire sweep. A final test yield exceeding 97% on two independent assembly lots was set as the criterion foracceptability of the technology in the manufacturing environment, based on inputs by the production group.Results of the assembly evaluations are summarized in Table II.
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