dec96a6 (1063268), страница 2
Текст из файла (страница 2)
Such a design would appreciably reduce wire sweep. A geometric progression algorithm has been developedfor the initial inline arrangement. The code for layout of progressive pads is complex because closed-form mathematicalexpressions are not available. This is covered in detail elsewhere.2Angle of ApproachWe now briefly examine the criteria for the selection of the convergence point alluded to above. Fig. 7 depicts wiretrajectories for two distinct bond pad layouts representing two extreme choices of convergence point. In both cases, thedesign of the leadframe is held constant. In Fig.7a, the convergence point is selected to be at the geometric center of the dieand in Fig.
7b, it is selected to be a large distance away from the geometric center of the die along the negative y-axis. Theangle between the wire trajectory and the bonding finger is defined as the angle of approach.Bond Fingers of LeadframeWiresRadially StaggeredBond Pads(b)(a)Fig. 7. Effects on angle of approach of two different bond pad layouts corresponding to twodistinct choices of convergence point. The angle of approach is the angle between the wiretrajectory and the bonding finger.
(a) Convergence point at the geometric center of the die.(b) Convergence point far from the geometric center along the negative y-axis.A large value of the angle of approach is likely to induce electrical shorts between a bonding wire and an adjacent bondingfinger, leading to lower assembly yields. It is therefore customary to specify a maximum allowable value for the angle ofapproach. HP’s manufacturing specification requires that the angle of approach always be lower than 10 degrees. Theapproach angles are unacceptably high for at least one wire in Fig.
7b, but are well within the specification in Fig. 7a.In the more general case, the approach angles are also a function of the leadframe design. As an example, in Fig. 8,a leadframe design is shown that is different from the one shown in Fig. 7, but the choice of convergence point for Figs. 8aand 8b is identical to that in Figs. 7a and 7b, respectively, that is, the convergence point is at the center of the die for Fig. 8aand at a large distance along the negative y-axis for Fig. 8b. However, in contrast to the case shown in Fig. 7, for the case inFig.
8 the approach angles are significantly lower for the choice of convergence point at a large distance along the negativey-axis than for the choice of convergence point at the center of the die. This is a consequence of the difference in theleadframe design between Figs.
7 and 8, and underscores the role of leadframe design in conjunction with the bond padlayout on the die in determining the approach angle in the general case.Bond Fingers of LeadframeWiresRadially StaggeredBond Pads(a)(b)Fig. 8. The same die pad layouts as in Fig. 7 but with a different leadframe design.The designs of typical leadframes used in real plastic packages are very close to the case depicted in Fig.
5, and therefore,low angles of approach are achievable by using the center of the die as the convergence point. This choice was made for thedesign of a test chip as discussed later.Article 6December 1996 Hewlett-Packard Journal5As a side note, it should be stated that in certain instances, the design of bonding fingers and the corresponding choice of aconvergence point for the radial staggering of bond pads on the die can be modified or customized to minimize wire length,and thus wire inductance, when electrical performance is critical. Such custom designs prove valuable in the case ofhigh-performance packages such as ball-grid arrays (BGAs).It can be shown that the theoretical minimum wire length with a zero angle of approach can be achieved by selecting theconvergence point at a location along the y-axis that causes the subtended angle for the corner pad to be the inverse cosineof the ratio of the effective bond pad pitch on the die to the effective bond finger pitch on the package.
The theoreticalanalysis of the general case has been performed,2 but is beyond the scope of this paper. The author has developed aniterative custom layout algorithm for the coupled layout of radially staggered bond pads on the die and bond fingers on thepackage that minimizes wire lengths for BGA packages, which typically provide fine-pitch bond finger capability and requirehigh electrical performance.2Implications for Pad Circuitry LayoutThe radially staggered bond pad configuration has one important consequence with regard to the layout of I/O pad circuitry,a point that is not initially obvious.
The bond pad is typically an integral part of a unit structure known variously as the padcell, the pad buffer, or the I/O pad. We will refer to it as the pad cell. As illustrated schematically in Fig. 9, the pad cellconsists of the I/O circuitry (such as pad drivers), the bond pad, and the ESD protection circuitry. In the conventional inlinebond pad design, the pad cell is called from a library and placed automatically along the die perimeter at a repeat distanceequal to the bond pad pitch. For an orthogonally staggered design, this procedure is minimally modified to include an x or yoffset for every other pad cell, the value of the offset being equal to the spacing between the two rows of bond pads of thestaggered configuration. However, if the bond pads have to be in a radially staggered configuration, each bond pad will notline up with the remaining portion of its associated pad cell (Fig. 10).
This means that the conventional pad cell placementmethodology has to be modified. It also means that an additional routing trace has to be added to connect the bond pad withits associated pad cell. These features are the subject of Article 7.ÌÌÌÌÌÌÌÌÌÌÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏÏESD StructureBond PadI/O Circuitry (Drivers, etc.)Fig. 9. Structure of an I/O pad cell.LimitationsOne limitation of the radially staggered design is that two rows of bond pads are required. The second row of pads uses upspace and accrues a penalty in silicon area utilization.
It is clear that in designs that are marginally pad-limited, a staggereddesign may not result in a net reduction of die size. In the following analysis, the important case of a marginally pad-limiteddesign is quantified, and a conditional expression is derived that can be used to determine whether a die size reduction canbe achieved by resorting to the radially staggered layout.Fig. 11 is a schematic illustration of a pad-limited IC design. In this figure, the region defined as white space is unused siliconarea resulting from the fact that the inner perimeter of the I/O pad ring falls outside the outer boundary of the core. Thiscondition occurs because the repeat distance for the pad cells (i.e., the pad pitch) is not small enough to pull in the I/O padring so that it hugs the core.
It can be shown that the size of the white space is independent of the pad height and isexpressible as:2W Pi (N/4) CArticle 6(5)December 1996 Hewlett-Packard Journal6315791113151719212325Bond Pads2143264586710812141618202224269 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26I/O Circuitry(a)13579111315171921231820222425Bond Pads21423645867108121416269 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26I/O Circuitry(b)Fig. 10. Illustration of bond pad shift caused by staggering. As a result of radialstaggering, the bond pads do not line up with the associated I/O pad cells.Pad CellPad RingHWhite SpaceCoreWCDieEdgeFig.
11. The presence of white space identifies a pad-limited IC design.where W is the size of the white space, Pi is the lowest qualified pitch (repeat distance of pads) for inline bonding, N is thepin count, and C is the size of the core.A pad-limited design is defined as a design that has a non-negative white space, that is, W 0, or, using equation 5,Pi(N/4) C.(6)While the effective repeat distance can be reduced using the radially staggered layout, additional space is required toaccommodate the second row of pads, as well as to accommodate a possible increase in pad height necessitated by thenarrowing of the pad cell.
This additional space is equal to the sum of the row-to-row spacing, d, and the increase in padheight, H, and can be pictured as a broadening of the pad ring. The size of the white space should be greater than theArticle 6December 1996 Hewlett-Packard Journal7broadening of the pad ring or the inner perimeter of the broadened pad ring will interfere with the core. This condition canbe expressed as follows:2d ) 2DH u Pi(N/4) * C.(7)If equation 7 holds for a given IC design, the design is deemed marginally pad-limited and a radially staggered arrangementwill not result in a die size reduction. However, if equation 7 does not hold, then the radially staggered layout will reduce thedie size and the layout methodology described above can be used to perform the layout.
In performing the radially staggeredlayout, the effective pitch for the initial inline arrangement should be selected so that the pad ring hugs the core. Thiscondition can be derived from equation 6 by replacing the inequality with an equality:Peffective + C(4/N).(8)If the design is severely pad-limited, the value of effective pitch calculated from equation 8 may turn out to be smaller thanthe smallest effective pitch supported even by the radially staggered bonding capability. In this case, the smallest supportedpitch should be used as the effective pitch.A further point should be made regarding the implications of the radially staggered design for higher pin counts. In general,the relative value of the penalty in silicon area associated with the second row of pads is diminished at higher pin countsbecause of the increase in the nominal value of the die size.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
