Advanced global navigation satellite system receiver design (797918), страница 26
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The PIF receiver was created in order toevaluate the performance of different variations in receiver architectures for the newsignals and novel acquisition and tracking techniques. In particular, the PIF receiverprovides a demonstration of the DE BOC receiver and enabled the detailed hardwareprocesses and performance of the DE technique to be defined, tested and analyzed.This project provides a PIF receiver architecture, which will provide the flexibility formany new variants of SSTL space receivers, while maintaining the same basebandarchitectural components.
Table 8-4 outlines the receiver versions suggested by thisresearch as forming the future range of SSTL GNSS receivers. All these receivers arebased on the baseband receiver architecture provided by the PIF receiver.178The SGR receivers and the PIF receiverTable 8-4, Predicted future SSTL receiver versionsReceiverversion1Signalsprocessed234Filterbandwidth2 MHzSamplingfrequency5.7 MHzGPS L1GPS L22 MHz5.7 MHzGPS L1 +Galileo E1GPS L5 +Galileo E5aGPS L1 +Galileo E1GPS L2GPS L5 +Galileo E5a +Galileo E5b4 MHz50 MHzGPS L120 MHz4 MHz120 MHz55 MHzApplicationSingle frequency, lowprecision, low bandwidthDual frequency, low precision,low bandwidthDual frequency, highprecision, high bandwidthTriple frequency ambiguityresolution, ultra-highprecision, ultra-highbandwidth,The PIF receiver is shown in Figure 8-11 connected to a Zarlink GP2010 RF frontend for GPS testing.
The IF GNSS signal is fed into the receiver’s 12-bit ADC(AD9430), which is a high-speed device from Analogue Devices capable of samplingfrequencies up to 210 Msps. Normally the ADC and AGC are provided by thereceivers RF front-end architecture. However, no RF front-ends suitable for thesignal bandwidth detailed in Table 8-4 were available during this research. Therefore,it was necessary to implement a high-speed, multi-bit ADC with large dynamic rangeand perform digital AGC in the correlator section.350ADC AD9430Processor ARM7 TDMIFPGA - XilinxVirtex IIInco mingIF signalRF front end Zarlink GP2010Figure 8-11, Prototype IF GNSS receiver179The SGR receivers and the PIF receiverA Xilinx Virtex II Field Programmable Gate Array (FPGA) was used to incorporateall correlator functions within a single high-density chip.
The FPGA is traditionallyused as a development platform, allowing the designer to re-program and debug theirprototype design prior to ASIC manufacture in large volumes (> 100,000 pieces).However, GNSS space receivers are rarely manufactured in large volumes and recentadvances in FPGA design, increasing capacity, improving radiation tolerance andreducing power consumption, make the FPGA a practical platform for GNSS spacereceiver designs. For space applications with extreme radiation environments, theFPGA code was designed with the intention of implementation in an Actel RTAXseries radiation tolerant chip, which is manufactured up to a two million gate capacity.FPGA’s are programmed using a Hardware Description Language (HDL) allowingthe following advantages in flexibility over the existing SSTL Space GPS Receiver(SGR) design.
Absorbing changes to GNSS signal structure – An FPGA can be reconfiguredto any future choice of PRN coding sequence, whether it is a stored memorycode, LFSR based or a concatenated coding scheme [Pratt et al 2004]. Flexible tracking techniques – The FPGA can be configured to allow adaptivetracking techniques for BOC, BCS and AltBOC modulation schemes. Architectures with massed correlator channels– The high density of modernFPGAs also allows more parallel search channels to be implemented thancurrent chipsets, vastly reducing the Time To First Fix (TTFF). This isespecially important for space users, where power restrictions result inintermittent usage. More tracking channels can also be useful for spaceapplications such as GNSS attitude determination and ocean reflectometry.
Fast Fourier Transform (FFT) search – Future GNSS implement longer PRNcodes than current civil systems. Combined with the large Doppler rangenecessary for space users, an FFT search becomes essential for futurereceivers (see Chapter 10). Therefore, a number of options for an FPGAbased FFT acquisition engine are being considered to reduce thecomputational load on the processor and reduce the receivers TTFF.An ARM7 32-bit Reduced Instruction Set Computer (RISC) is used to perform thehigh-speed receiver processes and low-rate navigational processes.
The180The SGR receivers and the PIF receivermicroprocessor of a GNSS receiver is required to perform rapid interrupt drivenupdates to sustain the receiver processes and maintain tracking loops for all receiverchannels. The processor must also perform navigational processes such as datademodulation, frame synchronisation, pseudorange and Doppler formation, allessential in order to form a navigational solution. The navigational processesgenerally occur at a relatively sedate speed (1-10 Hz), due to the low data rate ofGNSS signals, compared to the rapid update (1000 Hz) rate of the receiver trackingprocesses.The PIF receiver is designed to receive high bandwidth GNSS signals, up to 20 MHzbandwidth. The sampling frequency (50 MHz) is chosen in order to enable thereceiver to process signals from the SSTL IF GNSS signal generator and the SSTLMFUU signal generator.
The MFUU is capable of producing Galileo signals at an IFof 61.38 MHz. The frequency plan for receiving MFUU signals is shown in Figure8-12.Image-21.38-11.38-1.3801.3811.3821.3851.3861.3871.38Frequency (MHz)50MHz samplingFigure 8-12, Frequency plan for receiving MFUU signalsSampling the signal at a lower rate than the IF performs digitisation and frequencytranslation in a single step, this is called ‘sampling translation’. When undersampling the IF carrier in this way the designer must be careful to avoid aliasing withother sampled products. To choose a suitable under-sampling frequency first thesample rate fS, must satisfy the Nyquist criterion as follows.fS ≥ 2 × B8–29181The SGR receivers and the PIF receiverB is the two-sided signal bandwidth. Then to avoid aliasing while under-sampling,the sampling frequency must meet the following criterion [Lyons 2004].(2 × f 0 ) − B ≥mfS ≥(2 × f 0 ) + B8–30m +1where m is an arbitrary positive integer and f0 is the down-converted signal centrefrequency .
For under-sampling the prototype IF receiver the MFUU signal, with anIF of 61.38 MHz, m = 2 and bandwidth of 20 MHz Equation 8–30 becomes51.38 ≥ f S ≥ 47.58–31Therefore, f S = 50 MHz seems a good choice.The SSTL IF signal generator is capable of producing GNSS signals at an IF of20.46 MHz. If the receiver is sampling at 50 MHz we are now over-sampling thesignal and the highest frequency component faithfully represented without aliasing is25 MHz from Equation 8–29.
Therefore, the receiver can process signal from the IFsignal generator with bandwidths ±4.54MHz around the carrier or 9.08 MHz twosided bandwidth.8.4Correlator design for the PIF receiverThe FPGA correlator design is depicted in Figure 8-13. A 2-bit interface to a GPS RFfront-end is maintained for testing with GPS simulators and real signals. The digitalfront-end reduces the quantisation level of the signal to either a single bit with no gaincontrol or two bits with digital AGC dependant on the incoming signal level.182The SGR receivers and the PIF receiverFromADCDigital front end1 or 212Mean squarenoise calculationTrackingchannelChannelregistersTrackingchannelChannelregistersTrackingchannelChannelregisters2From GPSfront endSamplingClockPROCESSORINTERFACEAddressbus +controlsignalsData bus(16-bit)Systemregisters +time-basegeneratorFPGAFigure 8-13,Top level FPGA correlator architectureThe digitised input signals are fed to each tracking channel.
System registers are usedto provide global timing signals and debug modes. Similar to the GP2021 correlatortwo timing signals are sent to processor, a fast rate interrupt for accumulation valuesand a lower rate interrupt from measurement data. Tracking channels have a numberof associated channel registers, which store raw data from each correlation channel.A full description of the system and channel registers is given in Appendix G. Thetracking channel architecture is shown in Figure 8-14.
This is equivalent to the DEBOC correlator structure shown Figure 6-8.wIILaccumulatorwIIEaccumulatorwIIIaccumulatorwIQIaccumulatorReceivedGNSSsignalCarrier phaseregisterSub-carrierphase registerIICarrierDCOQLIESub-carrierDCOCodegeneratorTochannelregistersCode phasecountersQCarrier cyclecounterSub-carriercycle counterCode DCOEpoch countersWQQIaccumulatorwQIIaccumulatorwQIEaccumulatorwQILaccumulatorFigure 8-14, IF receiver tracking channel183The SGR receivers and the PIF receiverThe number of tracking channels available for the receiver is strongly dependant onthe size and architectural components of the FPGA chosen. For example, someFPGAs have built in multiplier blocks while others will have to synthesise multipliersusing logic. Therefore, the number of logic gates available to a specific chip onlygives a very rough estimate of device utilisation.
To provide proper comparison onemust look to into the actual hardware requirements of each channel. Table 8-5 showsthe hardware requirement for each tracking channel of the PIF receiver withcomparison against an equivalent PSK tracking channel operating at the samesampling rate.Table 8-5, IF receiver hardware requirements per tracking channelComponentsSizeMultipliers4 ×22 ×22 ×431 bits(frequency resolution =23.03 MHz)19 bits21 bits(carrier cycles in 100ms)20 bits(subcarrier cycles up to10.23MHz)20 bits(code chips up to10.23Mcps)11 bits(epoch counter 1ms epochs)31 bits(phase register)Digitally ControlledOscillators (DCO)AccumulatorsCountersRegistersNumber required per channelPSK4022(Carrier and CodeDCO’s)BOC + PSK8423 (Carrier, Subcarrierand Code DCO’s)41810111112(Carrier and CodeDCO phase)3 (Carrier, Subcarrierand Code DCO phase)The tracking channels were synthesised for the Xilinx Virtex II FPGA, implementinga single tracking channel and then 2 tracking channels.
Then the maximum numberof channels can be accurately estimated for this family of FPGAs. Table 8-6 showsthe FPGA utilisation for the Virtex II device. The figure of interest is the number of 4input Look-Up-Tables (LUT), which is the resource most readily consumed by anincrease in channels. From this we can estimate 19 PSK channels or 13 BOC in a1 million gate device, 39 PSK or 27 BOC in a 2 million gate device.184The SGR receivers and the PIF receiverTable 8-6, Xilinx Virtex II FPGA utilisation for PSK and BOC channelsLogic utilisationPSK1 channel2 channelsUsedAvailableUtilisationUsedAvailableUtilisationNumber of Slice Flip Flops68410,2406%112610,24010%Number of 4 input LUTs87010,2408%138410,24013%Number of bonded IOBs8817251%8817251%Number of MULT18X18s2405%44010%Number of GCLKs21612%21612%Number of DCMs1812%1812%Number of occupied Slices6535,12012%8335,12016%Logic utilisationBOC + PSKNumber of Slice Flip Flops1,04110,24010%1,67310,24016%Number of 4 input LUTs1,26610,24012%1,99610,24019%Number of bonded IOBs8817251%8817251%Number of MULT18X18s2405%44010%Number of GCLKs21612%21612%Number of DCMs1812%1812%Number of occupied Slices9415,12018%1,4875,12029%8.5Processor design for the PIF receiverAt a low level the processor must calculate the updates and take essentialmeasurements from the tracking loops.
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