Advanced global navigation satellite system receiver design (797918), страница 24
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A blockdiagram of the key components of the SGR is shown in Figure 8-1. The RF signal isreceived through the use of a Right-Hand Circularly Polarised (RHCP) antenna andfed directly into a Low Noise Amplifier (LNA), which effectively sets the noise floorfor the receiver. This is the most critical amplification stage, because at this point thesignal is below the thermal noise floor and any noise is amplified along with thesignal of interest.
Therefore, it is important that the noise figure of the LNA is assmall as possible (≤ 3 dB) while providing enough gain to raise the signal above thethermal noise level (20-30 dB). The LNA also provides filtering to protect againstsaturation from transmitters at other frequencies.164The SGR receivers and the PIF receiver125MHz35MHzLCfilterSAWfilterMemoryGP2021CorrelatorGP2015RF Front endLNAARM 60 orARM7TDMIProcessorTCXOInterfacesFigure 8-1, SGR receiver componentsThe GP2015 chip converts the GPS L1 signals (1575.42 MHz) to 4.309 MHz in threedown-conversion stages, filtering at each stage resulting in a IF bandwidth (1 dB) of1.9 MHz. The GP2015 then samples the signal at a rate of 5.714 MHz, whichtranslates an image of the negative frequency to 1.405 MHz, as depicted in Figure8-2.
All mixing frequencies and the sampling frequency are derived from a 10 MHzTemperature Controlled Crystal Oscillator (TCXO).Image-2.355-1.405-0.45500.4551.4052.3553.364.3095.26Frequency (MHz)5.714MHz samplingFigure 8-2, Frequency plan for GP2015The signal is quantised to a 2-bit representation with the mapping shown in Table 8-2.The IF signal is used to control the Automatic Gain Control (AGC) loop, which setsthe magnitude bit to be high 30% of the time and set the SIGN bit high approximately50% of the time.
The AGC loop is necessary to account for varying amplifier gainsand any cable losses. The time constant of the AGC loop is controlled via an externalcapacitor to the GP2015. This time constant must be considerably less than the165The SGR receivers and the PIF receiversettling time of the receiver’s tracking loops in order track variations in power levelwithout compromising the receiver operation.Table 8-2, 2-bit mapping by the GP2015Signal level-3-1+1+3Bit 0(SIGN)0011Bit 1(MAG)1001Percent in state(%)15353515In the absence of Continuous Wave (CW) interference the distributions across thefour digital levels given in Table 8-2 are held to within ±1% across a temperaturerange of -50ºC to 110ºC. However, in the presence of moderate CW interferers this isdegraded to ±10% [Zarlink 1999].
Figure 8-3 shows a histogram of an exampledistribution of sampled bits from the GP2015.Figure 8-3, Histogram of sampled signals from the GP2015The 2-bit quantised signal is fed to the GP2021 correlator, which is a dedicated 12channel GPS L1 C/A code correlator ASIC, shown in Figure 8-4. SGRs with 24channels effectively combine two GP2021 chips interfaced with a single processor.The GP2021 has a bus interface, an address decoder and a number of status registersto allow debugging of the correlator. The time-base generator produces twoimportant interrupt signals, which are used to ensure correct receiver operation. The166The SGR receivers and the PIF receiverfirst is a fast rate (<1 ms) interrupt for the accumulators (ACCUM_INT), this isnecessary to ensure that the essential information required for tracking the incomingsignal is read by the processor at least once every integration period.
The secondsignal is the measurement interrupt (MEAS_INT), which allows the processor to readthe raw measurement data. This interrupt is necessarily synchronized with the localoscillator to provide measurement data for the navigation solution. Both theseinterrupts are derived from and synchronized with the sampling frequency of5.714 MHz.Figure 8-4, GP2021 block diagram [Zarlink 2001]The incoming signal is latched and fed to the tracking modules, shown in Figure 8-5.Here, locally generated replicas of the carrier and code are multiplied onto the signaland the result is applied to the accumulator every sample period. At the end of theintegration period the result is latched onto a register to be read by the microprocessorbefore the next dump. The carrier and code signals are driven by Digitally ControlledOscillators (DCO), which can be updated instantaneously or at the start of eachintegration period.
The tracking module has two modes, acquisition and tracking. Asshown in Figure 8-5 these four results are equivalent to the correlation results derivedfor PSK in Equation 5-7 when the correlator is in tracking mode. In acquisition modethe tracking modules produce in-phase and quadrature correlation for a code sequence½ a chip earlier than the prompt code as in Equation 5-21.167The SGR receivers and the PIF receiverwQQ or wQEwQIwIIwIQ or wIEFigure 8-5, GP2021 tracking module diagram [Zarlink 2001]The processor uses the interrupt signals produced by the GP2021 to ensure timelyaccess to the correlation results and measurement data. Figure 8-6 depicts theinterrupt driven task structure of the SGR processor. The initialisation involvessetting up the software and starting the correlator channels running.
Afterinitialisation the software enables the software interrupts. The fast-rate tracking taskreads the accumulator values, estimates the navigational data state and updates allthree loops with new estimates of carrier and code phase. The lower-ratemeasurement task provides the detailed measurements required to form the navigationsolution such as reading the carrier, and code DCO values and the necessary countersin the correlator. Under these essential tasks priority can be given to the variousnavigational tasks.
The two low level tasks encompass the basic acquisition andtracking functions of the receiver and therefore are the tasks of interest for thisresearch. Knowledge of the low-level processor tasks and correlator architecture isnecessary in order to appreciate the receiver enhancements required by the futureGNSS signals.168The SGR receivers and the PIF receiverSTARTInitialisesoftwareEnableinterruptsInterruptNY≈ every 1msInterruptService Routine(ISR)≈ every 100msTRACKING TASKRead accumulators,update carrier and codeloopsNAVIGATIONALTASKSMEASUREMENTTASKMeasure carrier phase,cycle counts, codephase, etcFigure 8-6, Interrupt service routine for SGR receivers8.2SGR acquisition and tracking loopsThe implementation of PSK acquisition and tracking loops in the SGR gives us abasis on which to build and expand to realise the potential of the future GNSS signals.Therefore, in this section a detailed review of SGR’s acquisition and tracking loops isgiven, from which we form the basis for the PIF receiver.In order to judge whether a signal is present or absent the theoretical noise floor of thereceiver must be calculated.
While tracking is achieved this value can also be used toestimate the signal to noise ratio of the received signals. The theoretical noise floor ofthe receiver can be determined from statistical analysis of the correlation outputs withonly thermal noise present at the receiver input. Table 8-3 shows the mean squareaccumulation values taken over one IF carrier cycle.169The SGR receivers and the PIF receiverTable 8-3, Mean square accumulation values over one carrier cycleInput signalResult of sine carrier DCO mixing over one cyclefrom ADCMeansquare+33663-3-6-6-322.5+11221-1-2-2-12.5-1-1-2-2-112212.5-3-3-6-6-3+3+6+6+322.5Combining the mean square accumulation values from Table 8-3, with the statisticaldistribution of the input signal from Table 8-2, results in the following theoreticalnoise floor value for one accumulation period T.NFSGR = 2 × (0.3 × 22.5 + 0.7 × 2.5) × f s × T = 97,1428–1The factor of 2 accounts for the combination of two accumulation values (wII and wQI)that are used to determine the signal power, both of which contribute to the theoreticalnoise floor of the receiver.
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