Advanced global navigation satellite system receiver design (797918), страница 25

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Figure 8-7 shows the noise floor of the SGR receiver withno signal present, the mean square of the I/Q points agrees strongly with the derivedtheoretical noise floor.Figure 8-7, SGR noise floor with no signal presentThe SGR uses a traditional time-domain search across two dimensions: code delayand carrier Doppler. The code search is performed by programming the code DCO to170The SGR receivers and the PIF receiverrun slightly faster than the predicted rate (0.8 chip per msec), allowing the receivedand replica codes to slide past each other with time. The presence or absence of asignal is determined by through the correlation power given by222wSSGR = wII + wQI + wIE + wQE28–2The SGR sums the correlation power of two identical PRN codes, one a ½ chip earlierthan the other.

This allows a search rate of 0.8 chips per msec with a minimumcorrelation gain of only -0.7 dB from the peak value.ΛC, Λ , ΛEΛC, Λ , ΛEa)b)Figure 8-8, Plot combined search correlation wSSGR (shown in blue)Signal presence in the SGR is declared if the correlation power is greater than athreshold, which is nominally set to twice the receiver’s theoretical noise floor. Thecarrier is searched in 500 Hz frequency bins. This corresponds to a minimumcorrelation gain of –4 dB compared to the peak.The SGR tracking loops were originally based on the Mitel GPS Architect software,which was designed for the ARM60 processor. The Architect code uses a 2nd orderFLL with the cross-product frequency discriminator described in Equation 5-14.

Inorder to enable precise delta pseudorange, integrated Doppler measurements andapplications such as attitude determination through GNSS a PLL is required. In 1999the SGR was adapted to use a FLL/PLL combination to acquire and track GPS in171The SGR receivers and the PIF receiversatellite orbits although it retains the ability to solely use the FLL for more robustapplications.The FLL/PLL combination uses a 1st order frequency discriminator to reduce thecarrier frequency error to within the capture range of the PLL. The FLL employs twostages; acquiring the signal with a large loop bandwidth (31.25 Hz) and reducing thefrequency error with a narrower loop bandwidth (1 Hz) FLL. The transition is madeto the PLL when the estimated frequency error is less than 1 Hz.

The SGR FLL usesa four quadrant discriminator which determines a frequency error term bydifferencing adjacent 1ms observations, assuming no data transitions have occurred.The change between adjacent I and adjacent Q samples can be written as∆I = I k − I k −18–3∆Q = Qk − Qk −1The sign of the current correlations and their magnitudes provide the choice and signof the error term as follows.∆Qfor I k > Qk , I k − ∆Q for I k > Qk , I keω = for I k ≤ Qk , Qk ∆I − ∆I for I k ≤ Qk , Qk>08–4≤0>0≤0A block diagram of a first order FLL is shown in Figure 8-9.eφ(t)ω0t + φ(t)+−eω(t)sKFDω0t + φ^(t)KDCOs++1/T11sω0Figure 8-9, First order FLL172The SGR receivers and the PIF receiverFrom Figure 8-9 the loop phase estimate can be identified as follows.ˆ = K FD × K DCO × EΦωs 2T18–5T1 is the time constant of the first order loop, K FD is the gain of the frequencydiscriminator and K DCO is the carrier DCO gain.

This can also be expressed in termsof phase error eφ as follows.()ˆ = sK FD K DCO × Φ − Φˆ = K FD K DCO × EΦφ2s T1sT18–6In order to convert to the digital domain there is no unique mapping, but a commonlyused approximation is [Jordan and Smith 1997]s≈()1 s∆1e − 1 = ( z − 1)∆∆8–7where ∆ is the sampling or update interval of computationˆ = K FD K DCO ∆ × EΦφ(z − 1)T18–8or(z − 1)Φˆ = K FD K DCO ∆ × Eφ8–9T1(1 − z )Φˆ = z−1−1K FD K DCO ∆× EφT1which allows identification with the theory given in Chapter 5 for the FLL, whichgives a digital loop update equation of the formeφ ← eφ + eω8–10φˆ ← φˆ + k1 × eφwherek1 =K FD K DCO ∆T18–11173The SGR receivers and the PIF receiverThe natural loop frequency ωn and loop bandwidth BL can then be calculated asfollows.ωK FD × K DCO, BL = nT14ωn =8–12FLL loop bandwidths of 31.25 Hz and 1 Hz correspond to loop filter values (T1) of1/8 and 1/256 respectively. The receiver starts with the wide band filter and if carrierlock is declared the narrow band filter is used.

The transition between FLL and PLLoccurs when the frequency error, eω is estimated to be less than 1 Hz.The SGR PLL is a 2nd order loop, a block diagram is shown in Figure 8-10.eφ(t)ω0t + φ(t)+−T2KPD^ω0t + φ(t)1sKDCOs++++1/T1ω0Figure 8-10, Second order PLLThe phase estimate of the second order PLL can then be written as follows.ˆ = K PD K DCO ×  T + 1  × Φ − ΦˆΦ2sT1s1K K= PD DCO ×  T2 +  × EφsT1s()8–13T1 and T2 are time constants, K PD is the gain of the frequency discriminator and K DCOis the carrier DCO gain. Then converting to the digital domain using theapproximation given in Equation 8–7 gives174The SGR receivers and the PIF receiverˆ =ΦKφ ∆∆ ×  T2 + × Eφ(z − 1)T1 z −18–14or rearrangingKφ ∆2KT∆ˆ(z − 1)Φ =fφ + φ 2 EφT1T18–152KT∆−1 Kφ ∆ˆ1− z Φ = zfφ + z −1 φ 2 EφT1T1(−1)whereFφ =Eφ(z − 1)8–16which allows identification with the theory given in Chapter 5 for the FLL, whichgives a digital loop update equation of the formf φ ← f φ + eφ8–17φˆ ← φˆ + k1 × f φ + k 2 × eφwherek1 =K FD K DCO ∆2T1k2 =K FD K DCOT2 ∆T18–18The filter coefficients T1 and T2 set the natural loop frequency ωn , the damping factorξ and loop bandwidth BL as followsωn =(K D × K DCOT × ωn1+ 4×ξ 2, ξ= 2, BL = ωn2(8 × ξ )T1)8–19The designer must consider a trade off at this point between narrowing the loopbandwidth to reduce the thermal noise jitter and widening the loop bandwidth in orderto track accelerations.

This depends strongly on the dynamic environment thereceiver will operate within. Also, in practical systems there is the consideration ofcomputational load, the SGR loop design chooses filter values to the nearest power of2 to reduce microprocessor burden. The effect of this is to shift the loop parametersaway from the desired values. Therefore, if the response parameters of the loop are175The SGR receivers and the PIF receivercritical, floating-point calculations must be performed within high-speed trackingprocesses.The maximum rate of change that can cause loss of lock is can be approximated by[Gardener 1979]∆ω& max = ωn28–20The SGR loops are designed for a maximum acceleration of 60 Hz/s, however theapproximation to power of two calculations reduces the maximum to 52.1 Hz/s.The DLL in the SGR uses the dot product discriminator, which has the followingerror function (repeat from Equation 5-17).eτ = wII × wIQ + wQI × wQQ8–21This discriminator is used in a first order loop as described in Equation 8–10.

TheSGR code DLL has a loop bandwidth of 0.25 Hz. It is only possible for the DLL tobe first order and employ such narrow loop bandwidths because the DLL receivesDoppler aiding from the carrier loop. The carrier tracks the frequency and/or phase ofthe incoming signal; this is a second order loop and tracks accelerations in the system.The estimated Doppler frequency of the carrier can then be applied to the DLL, withsufficient scaling to effectively remove the dynamics from the loop and allow firstorder operations.The scaling Kφ, is simply the ratio of the code frequency to the L-band carrierfrequency (1.023 MHz / 1575.42 MHz for standard GPS).

If the carrier update is φˆthen the loop update equation with carrier aiding becomesτˆ = τˆ + kφ × fφ + kτ × eτ8–22176The SGR receivers and the PIF receiverwherekτ =K CD K DCO ∆T18–23Where T1 is the time constant of the first order loop, K CD is the gain of the codediscriminator and K DCO is the code DCO gain.The SGR receiver uses a number of indicators to monitor the quality of the code andcarrier tracking. The quality of the code tracking is computed by taking runningaverage of the correlation power. The SGR code lock indicator can be written as() w 2 + wQI 2 − CdLi CdLi = CdLi +  II2568–24The signal to noise ratio can then be estimated by comparing this filtered value to thereceiver’s noise floor as follows. CSNRSGR = 10 × log dLi  NFSGR (dB − kHz )8–25This represents the signal to noise in a 1 kHz bandwidth (T = 1 ms), to convert tostandard units of carrier to noise in a 1 Hz bandwidth simply use the followingtranslation.C1= SNRSGR + 10 × log N0T (dB − Hz )8–26While the receiver is tracking in FLL mode the quality of the carrier frequencytracking is computed by looking at adjacent I and Q samples (assuming no datatransition).

The SGR carrier lock indicator while running a FLL is given by177The SGR receivers and the PIF receiver (w × wQI '+ wQI × wII ') − CrLi FCrLi F = CrLi F +  II40968–27where wII ' and wQI ' are the previous correlation results.When the receiver is in PLL mode the quality of the carrier phase tracking iscomputed by subtracting the correlation power in the quadrature channel from the inphase correlation power. The SGR carrier lock indicator while running a PLL isgiven byCrLi P = CrLi P() wII 2 − wQI 2 − CrLi P +40968–28The current range of SGR receivers have been very successful and still offer anattractive product for most space applications. However, the receiver is restricted tothe capabilities of the now aging Zarlink GPS chipset and requires a more flexiblearchitecture to gain the advantages of future GNSS systems.8.3PIF receiver hardware and frequency planEvaluation of receiver acquisition and tracking algorithms for future GNSS signals isdesirable at an Intermediate Frequency (IF) due to the current lack of RF front-endarchitectures suitable for these signals.

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