Advanced global navigation satellite system receiver design (797918), страница 27
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In addition, the navigational data must also bedecoded in order to perform a navigational solution.When acquiring and tracking PSK signals the processor commands the correlator inthe similar manner as the SSTL SGR receiver. The signal search process isperformed using a serial code slew, shifting the code in half chip increments. Thefrequency is searched in bins 12×THz bins, where T is the integration period.Comparing the correlation given in Equation 8–2 to a threshold value it assesses thepresence or absence of a PSK signal. When a signal is declared present the carrierDCO value is initialised with the frequency of the current search bin and the codeDCO is initialised with the code offset plus the current frequency offset (Doppler)185The SGR receivers and the PIF receiverscaled down to the code frequency.
The signals are then acquired using a FLL/PLLcombination for carrier tracking and a DLL for the code tracking. The quality oftracking is assessed using the formula given in Equation 8–24 for code tracking,Equation 8–27 for frequency tracking and Equation 8–28 for phase tracking.The PIF receiver acquisition and tracking sequence for PSK signals is shown inFigure 8-15.Called at least oncea code epochStartNewdump?NReturnYYIfStatus =Code lock ?NUpdate loopsUpdate lock indicatorsStatus = SearchYStatus = SearchIfCdLi < Lossthreshold?NNStatus = Code lockIfSlew count =Code length(half chips)?YMove to next Doppler binUpdate Carrier DCO DopplerUpdate Code DCO DopplerSlew count = 0NIfCrLi > Carrierthreshold?YStatus = Code and Carrier lockIfSearchcorrelation >Search threshold?NSlew code a half chipSlew count ++YStatus = Code lockInitialise Carrier DCOInitialise Code DCOInitialise lock indicatorsCdLi = Loss thresholdCrLi = 0CdLi – Code LockindicatorCrLi – Carrier LockindicatorReturnFigure 8-15, Interrupt driven acquisition and tracking for PSK signals186The SGR receivers and the PIF receiverWhen searching for BOC signals the carrier and code bin width is unchanged fromPSK.
Despite this, as described in Section 5.3 we must create a single correlationpeak by combining the in-phase BOC correlations with the quadrature BOCcorrelations as follows.222wSBOC = wIII + wQII + wIQI + wQQI28–32The IF receiver acquisition and tracking sequence for BOC signals is shown in Figure8-16.
During the search process the BOC sub-carrier is kept locked to the code, bothsignals being derived from a common DCO. When a signal is detected, the carrierDCO is initialised with the value of the current search bin. The sub-carrier DCO isinitialised with an appropriate Doppler scaled down to the sub-carrier frequency. Thecode DCO is initialised with the code offset plus estimated Doppler scaled down tothe code frequency. A command is then sent to the correlator to unleash the subcarrier.
Subsequently the timing of the correlating sub-carrier is based purely on thesub-carrier DCO and is independent of the state of the code DCO. A Sub-carrierLocked Loop (SLL) must also now be operated to maintain lock on the signal. Thequality of the sub-carrier phase tracking is computed by subtracting the correlationpower in the quadrature BOC correlations (wIQI and wQQI) from the power of the inphase correlations (wIII and wQII).
This is similar to the PLL lock indicator where thecontribution of the quadrature correlation is monitored to observe any deviation fromzero. The sub-carrier lock indicator used in the IF receiver is given by[() ()] w 2 − wIQI 2 + wQII 2 − wQQI 2 − SbLi SbLi = S bLi + III40968–33The quadrature carrier correlations wQII and wQQI are included if operating withincoherent FLL carrier tracking.187The SGR receivers and the PIF receiverCalled at least oncea code epochStartNewdump?NReturnYYUpdate loopsUpdate lock indicatorsIfCdLi < Lossthreshold?YStatus = SearchNIfStatus =Code lock ?NStatus = SearchLock sub-carrierIfSlew count =Code length(half chips)?YMove to next Doppler binUpdate Carrier DCO DopplerUpdate Sub-carrier DCO DopplerUpdate Code DCO DopplerSlew count = 0Status = Code lockNIfSbLi > Subcarrier threshold?YStatus = CodeandSub-carrier lockNIfCrLi > Carrierthreshold?YStatus = Code, Sub-carrier andCarrier lockNIfSearchcorrelation >Search threshold?NSlew code a half chipSlew count ++YStatus = Code lockInitialise Carrier DCOInitialise Sub-carrier DCOInitialise Code DCOInitialise lock indicatorsCdLi = Loss thresholdSbLi = 0CrLi = 0Unlock sub-carrierCdLi – Code LockindicatorSbLi – Sub-carrierLock indicatorCrLi – Carrier LockindicatorReturnFigure 8-16, Interrupt driven acquisition and tracking sequence for BOC signalsThe update equations for the carrier and code loops are based on the SGR loops,detailed in Section 8.2.
As shown in Chapter 6 the SLL can be kept as a first orderloop if receiving Doppler aiding from the carrier loop. The update equation for theSLL is then equivalent to the DLL update (Equation 8–22) with appropriate scaling ofthe Doppler estimate to the rate of the sub-carrier. Table 8-7 lists the loop parametersand loop update equations used in the IF receiver.188The SGR receivers and the PIF receiverTable 8-7, Loop parameters and update equationsLoopUpdate equationReferenceLoop bandwidth - BL ,Damping factor - ξFLLeφ ← eφ + eωEquation 8–10BL =1 Hz (narrow)φˆ ← φˆ + k1 × eφPLLf φ ← f φ + eφBL =31.25 Hz (wide)Equation 8–17BL =14.72 Hzξ = 1.04φˆ ← φˆ + k1 × f φ + k 2 × eφSLLτˆ* = τˆ* + kφ × fφ + kτ × eτ *Equation 8–22BSLL =1 HzDLLτˆ = τˆ + kφ × fφ + kτ × eτEquation 8–22BDLL =1 HzThis chapter has given a detailed description of the hardware and software of theSSTL SGR receivers and the PIF receiver. The PIF receiver, which was createdduring this research, provides a demonstration platform for the DE BOC trackingtechnique.
The changes to hardware correlator design and software-tracking processrequired by future GNSS signal have been outlined in this chapter. In particular theadaptations required to implement the DE BOC tracking technique have beendescribed. The FPGA-based correlator architecture provides future SSTL receivers aflexible core capable of receiving and processing the future GNSS signals. Theextension of this concept to a single FPGA-based GNSS correlator and processor isshown in Chapter 10. Testing of the PIF receiver and the DE BOC tracking techniqueis shown in the following chapter.1899Prototype receiver testing and resultsThis Chapter describes the testing strategy and the results derived from the PIFreceiver. Firstly, the verification of the receiver design for existing GPS PSK signalsis described.
This was achieved using the SSTL Spirent STR4760 GPS simulator andlive GPS signals from space. Secondly, a description of testing of PSK and BOCsignals using the IF signal generator is given. The implementation of the DE BOCtracking technique is emphasised with in-depth details of the formation of DEmeasurements and performance testing of this technique. The results are comparedwith theoretical predictions with a detailed explanation of the receivers tracking loopsnecessary for this comparison.9.1AGC and GPS testingEvaluating and verifying the receiver performance for PSK signals is simplified dueto the current availability of GPS simulators. SSTL have three such simulators,manufactured by Spirent Communications (STR4760 (16 channels), STR4500(12channels), STR4775(1 channel)), all of which are hardware simulators capable ofproducing representative RF GPS signals with accurate modelling of the receiverenvironment.
A rooftop antenna was also used to verify receiver operation with liveGPS signals. However, for receiver evaluation the simulator provides far moreflexibility than live signals. The simulator can be pre-programmed with a scenariodescribing the movement of the receiver and GPS constellation. Changes in receiverattitude, accelerations and atmospheric variations can also be pre-programmed and thesimulator has the capability to operate in a single channel mode where satellite PRNcode, signal strength and Doppler offsets can be varied manually.The Zarlink GP2010 RF front end has an IF output (4.309 MHz) suitable for feedingdirectly to the ADC of the IF receiver. Therefore, this front end was selected toenable testing with the SSTL simulators and real live signals. The lab setup is shownin Figure 9-1.
A PC is used to download, run and monitor the output of the receiverthrough the serial UART interface.190Prototype receiver testing and resultsLive signalsPCSpirentSTR4760GPS L1 C/ASimulatorPrototype receiverFigure 9-1, Prototype receiver GPS PSK test setupThe ADC accepts signals up to 1.3 V peak-to-peak, centred at ground, with 50 Ωtermination in low gain mode and signals of 0.7V peak-to-peak in high gain mode.The GP2010 provides a peak-to-peak voltage of between 0.09 V and 0.18 V into a 50Ω termination.
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