Advanced global navigation satellite system receiver design (797918), страница 30
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Therefore, the SOC generally refers tothe baseband section, providing a correlator and processor with in single ASIC,although a few modern ASICs have succeeded in combining the RF and basebandsections.Traditionally FPGAs have been used for development and prototype work because oftheir ability to be reprogrammed.
However, modern FPGA architectures, such as theVirtex 5 from Xilinx [Xilinx 2005], focus on reducing power consumption. Also,207Single chip GPS and Giove-A receivermany FPGA families prove radiation tolerant designs suitable for the harshenvironments of space applications. SSTL have for many years operated bothradiation tolerant and commercial one-time programmable Actel FPGAs in space.Re-programmable Actel ProASIC FPGAs have also been flown by SSTL and theyhave plans to use the Xilinx Virtex 4 family on future missions. Advances in FPGAtechnology now provide high-density low-power architectures capable ofconsolidating the correlator and processor architectures in a single chip.
Therefore, inorder to break the dependence of SSTL receivers on ASICs and provide a designsuitable for the new generation of GNSS signal a single-chip FPGA solution isdesirable.FPGA families of particular interest are those developed to be compatible with softcore processor designs. Actel have developed an ProASIC FPGA with the option of a32-bit ARM7 TDMI soft-core processor. SSTL currently use the ARM7 in theirSGR-05 receiver range and therefore this option was desirable in order to port thereceiver code to the FPGA.
However, this design was not available during thisresearch and therefore other soft-core processors were considered.The LEON project was introduced in October 1997, at European Space Research andTechnology Centre (ESTEC). This internal project aimed to develop a highperformance 32-bit soft-core processor for future European Space Missions.
Thesemissions required a high-performance low-cost processor and with unrestricted longterm availability of both components and software tool-chains. The result was theLEON soft-core processor, which is free to use under a General-Purpose Licence(GPL). The third version of this core is called the LEON3 [Gaisler 2006].
Althoughthis version of the core is still under a GPL its support is managed by GaislerResearch, who provide a complete range of supporting tools including compilers,simulators and debug applications. The architectural components of the LEON3 softcore are shown in Figure 10-1. An attractive feature of the LEON3 is the ability toefficiently configure the core components as desired, reducing the FPGA resourceconsumption. The LEON3 includes a high-speed 32-bit data bus conforming to theAdvanced Microprocessor Bus Architecture (AMBA) specification, which is ideal forconnection to high performance units such as a GNSS correlator.
An optional208Single chip GPS and Giove-A receiverfloating-point unit is available which is attractive for numerically intense applicationssuch as FFT acquisition, Kalman filtering, attitude and orbit determination.Figure 10-1, LEON3 architectural components [Gaisler 2006]Supported by SSTL and SSC an undergraduate student project was carried out byAntonio Lopes to integrate a basic GPS correlator code with the LEON3 processor ina Xilinx Spartan 3 FPGA.DebugsupportunitLEON3ProcessorSerialdebuginterfaceRS232GNSSCorrelatorHigh performance busRF front endinterfacePeripheral busBuscontrollerMemorycontrollerBridgeSerialinterfaceTimersRS232Watch dogSpartan 3 FPGARead-OnlyMemoryRandom-AccessMemoryFigure 10-2, LEON3 processor with GNSS correlator209Single chip GPS and Giove-A receiverThe GPS correlator combined with the LEON3 design was synthesized for a XilinxSpartan 3 FPGA and implemented on the NuHorizons SP3-1500 development board.Figure 10-3 shows the single-chip receiver connected during testing with the GPSsimulator.Xilinx Spartan 3FPGANuHorizonsdevelopmentboardZarlink GP2015RF front endFigure 10-3, GPS testing of the single-chip receiverSoftware was written to perform the basic GPS search, acquisition and trackingfunctions mirroring those implemented in the SGR receivers.10.2 RF front-ends for the single chip receiverVerification of the single-chip receiver with GPS signals was achieved using theZarlink GP2010 RF front-end, currently used in the SGR receivers.
The GP2015mixes down the incoming L1 band carrier (1575.42 MHz) to a 2-bit sampled IF of1.405 MHz (see Figure 10-4). The GP2010 is suitable for the GPS C/A signal, whichhas a PSK-R(1) modulation. However, the low sampling rate and tight IF filter(2MHz bandwidth), is insufficient to process the main lobes of the Galileo L1 B+Csignal which has a BOC(1,1) modulation.210Single chip GPS and Giove-A receiverImage-2.355-1.405-0.45500.4551.4052.3553.364.3095.26Frequency (MHz)5.714MHz samplingFigure 10-4, Frequency plan for GP2015A major advantage of an FPGA-based GNSS receiver is its flexibility, which enablesthe designer change the RF front-end architecture with no change to the receiver’scorrelator hardware.
Changing the RF front-end requires adapting the sampling rateand IF carrier frequency of the GNSS correlator. Increasing the sampling frequencyof the correlator requires increasing the size of each channel’s accumulators and mayincrease the size of the DCO phase registers. Therefore, increasing the samplingfrequency reduces the number of channels achievable in a specific FPGA.In order to process the Galileo BOC(1,1) signal with the single-chip receiver we useNemerix NJ1006A RF front-end [Nemerix 2005]. This modern front-end ASICmixes L1 band signal down to a 2-bit sampled IF of 4.188 MHz with a 3.5 MHz 3 dBfilter bandwidth and a sampling frequency of 16.367 MHz (see Figure 10-5).
Despitealmost tripling the sampling rate of the GP2010 front-end the power consumption ofthe modern NJ1006A is actually one tenth of the GP2010, illustrating the advances inlow-power RF front-end architectures.211Single chip GPS and Giove-A receiverImage-5.938-4.188-2.43802.4384.1885.93820.5518.822.3Frequency (MHz)16.367 MHz samplingFigure 10-5, Frequency plan for Nemerix NJ1006A RF front end10.3 Receiving the Galileo BOC(1,1) E1 signalDemonstration and evaluation of the acquisition and tracking of the GPS C/A codesignals was achieved using the SSTL 16-channel GPS simulator rooftop antenna.The Galileo signal E1 contains three components A, B and C, which are combinedusing Interplex modulation with a modulation index m = 0.6155.
Substitutingm = 0.6155 into Equation 7–8 the Galileo E1 signal with normalized power can bewritten as follows.[]12 (bE1B (t )d (t ) − bE1C (t ) ) cos(ω L1t )3+ [2(bE1 A (t )d (t ) ) + bE1 A (t )bE1B (t )bE1C (t )]sin(ω L1t )S E1 (t ) =10–1The open service (B + C) signals are to be transmitted with either a BOC(1,1) orMBOC(6,1,1/11) modulation. It is important to note that the data component, B andthe pilot component, C are transmitted on the same carrier component. Themodulation I/Q plot shown in Figure 10-6 provides an insight into the effect of theinterplex modulation.
The inter-modulation term is used to control the level of thequadrature contribution in order to maintain a constant amplitude. However, from thereceiver point of view it is unlikely that the receiver has the capability or has access tothe E1 A component, which is a PRS signal. Looking from a receiver perspective,without the A component there is no quadrature contribution as shown in Figure 10-7.212Single chip GPS and Giove-A receiver(bE1A (t ) = +1, bE1B (t ) = bE1C (t )) bE1 A (t ) = +1, bE1B (t ) = −1, bE1C (t ) = +1 bE1 A (t ) = +1, bE1B (t ) = +1, bE1C (t ) = −1Q10.750.50.25I-1-0.75-0.5-0.250.250.50.751-0.25-0.5 bE1 A (t ) = −1, bE1B (t ) = −1, bE1C (t ) = +1 bE1 A (t ) = −1, bE1B (t ) = +1, bE1C (t ) = −1-0.75-1(bE1 A (t ) = −1, bE1B (t ) = bE1C (t ))Figure 10-6, I/Q plot of Galileo E1 signal with code states (ignoring data modulation, m = 0.6155)(bE1B (t ) = bE1C (t ) )1Q( bE1B (t ) = +1, bE1C (t ) = −1)0.75(bE1B (t ) = −1, bE1C (t ) = +1)0.50.25I-1-0.75-0.5-0.250.250.50.751-0.25-0.5-0.75-1Figure 10-7, I/Q plot of Galileo E1 signal from the receiver perspective(ignoring the A component and data modulation, m = 0.6155)For the Galileo E1 signals 55.5& percent of the transmitted power is given to the Acomponent and inter-modulated product.
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