Advanced global navigation satellite system receiver design (797918), страница 29
Текст из файла (страница 29)
The carrier to noise of the signal generator given by Equation 9–6 whilegenerating a PSK-R(1) signal, is compared with the estimated carrier to noise fromthe IF receiver in Figure 9-8. The measured implementation loss is the sum of lossesdue to a single-bit IF up-conversion, digital to analogue conversion, RF cable loss andthe conversion back from analogue to a 2-bit digital signal. After correcting for the198Prototype receiver testing and resultsimplementation loss the estimated carrier to noise can be seen to very accurately agree(0.24 dB r.m.s.) with the corresponding theoretical values.Figure 9-8, Comparison of PIF receiver estimated and theoretical carrier to noise densities forPSK-R(1)In order to validate these results we measure the code tracking jitter at various C/N0levels and look for agreement with established theoretical values. The code trackingjitter can then be evaluated by examining the subtraction of pseudorange from theintegrated carrier phase across a data-set of sufficient size (see Figure 9-6).
Figure9-9 shows a comparison of the code tracking measured from the receiver with thetheory given for a coherent PSK DLL given in Equation 4–16. Each point on thefigure represents a dataset of 8-10 minutes taking readings at 1 Hz. The receiver’scode loop bandwidth is set to 1 Hz.199Prototype receiver testing and resultsFigure 9-9, Comparison of PIF receiver estimated and theoretical code tracking jitter forPSK-R(1)9.2BOC measurements and testingThis section describes the demonstration of BOC signal acquisition and tracking usingthe PIF receiver.
The measurements taken by the PIF receiver while processing BOCsignals from the IF signal generator are detailed and results given.A 2-channel receiver was configured with the first channel implementing the DEBOC tracking loops (see Chapter 6) and the second channel using the BJ algorithm(see Section 5.4). This allows cross checking between the channels to ensure correcttracking states.
Acquisition is achieved by the SCC technique (see Section 5.3),which provides a single peak for robust signal acquisition.Assuming proper synchronisation with the incoming signal using the DE BOCreceiver, the transmit time of the signal, TTi(n) can be determined. Similarly to PSKtransmissions this is achieved by combining the values of the data counters and epochcounters, half chip counter and code DCO phase ( τ DCO ), which can be written asfollows.200Prototype receiver testing and resultsTτ i (n) = (LD × X D ) +1 X× X E + HCLE N HC + τ DCO(ms )9–7At the time of measurement this is entirely equivalent to the delay estimate from theDLL loop of the DE BOC receiver, denoted τˆ .
The SLL delay estimate, which locksonto an ambiguous integer BOC sub-chip, can be formed using the sub-carrier DCO*phase ( τ DCO) as follows.Tτ *i (n) = (LD × X D ) +1 X× X E + HCLE N HC * + τ DCO(ms)9–8The more precise SLL estimate can then be corrected by the DLL estimate to deliverthe best estimate of received signal transit time as follows. T (n) − Tτ i (n) × TSTTi (n) = Tτ *i (n) − round τ *iTS(ms )9–9TS is a sub-chip. Alternatively the more precise SLL estimate can be used incombination with the values of the sub-carrier cycle counter, XSC to provide anintegrated sub-carrier phase (ISCP) measurement as follows.ISCPi = (X SC + τ ′* DCO − τ *DCO )× λSC( m)9–10τ ′* DCO is the current SLL delay estimate, τ * DCO is the previous SLL estimate and λSCis the sub-carrier wavelength.As shown in Section 6.5 any distortions in the received BOC signal can compromisethe reliability of receivers operating the BJ algorithm.
In the DE BOC receiver anasymmetric correlation function causes a sub-carrier to code offset, which results in anon-integer sub-chip offset between the DLL and SLL delay estimate. A small offsetbetween the DLL and SLL estimates has been observed on the PIF receiver whentracking signals from the IF signal generator. We believe this is due to distortion in201Prototype receiver testing and resultsthe signal generator causes an asymmetric BOC correlation function. Asymmetry hasbeen observed from both the BOC(1,1) and BOC(15,2.5) [Falcone et al 2006] signalsfrom Giove-A.The DE BOC receiver can measure and therefore correct for this asymmetry. Figure9-10 shows the measured difference between the DLL estimate and corrected SLLestimate (corrected by integer sub-chips).Figure 9-10, Measurement offset due to asymmetric BOC(1,1) signalOnce the DLL and SLL delay offset has been measured the receiver can be calibratedfor each transmission.
The transmit time corrected for asymmetry in the receivedsignal can then be written as follows. T (n) − Tτ i (n) − δ Si × TSTTi (n) = Tτ *i (n) − round τ *iTS(ms )9–11δ Si is the asymmetry correction for the satellite i. A typical output of the PIF receiverwhile processing a BOC(1,1) signal is shown in Figure 9-11.202Prototype receiver testing and resultsChannelDopplerfrequencyoffsetEstimatedsignal-tonoise ratioDLL delayestimate (m)Integrated carrierphase (m)Corrected SLLdelay estimate(m)Loop lock indicators(Code, Sub-carrier, Carrier)Figure 9-11, Typical PIF receiver display for BOC signalsThe IF signal generator was configured to produce a BOC(1,1) modulated signal. Forsimplicity the same PRN codes were generated as the PSK case, a 1023 chip Goldcode with a 1 ms repeat period (C/A code SV1).
The PIF receiver was configured tosearch for the BOC(1,1) signal in half-chip code steps and 500 Hz frequency binsusing the SCC BOC search technique. Both the loop bandwidth of SLL and DLLtracking loops of the DE BOC receiver channel were set to 1 Hz.We repeat the test of Figure 9-8, comparing the receiver estimated carrier to noisedensity against theoretical predictions. The carrier to noise of the signal generatorgiven by Equation 9–6 while generating a BOC(1,1) signal, is compared with theestimated carrier to noise from the IF receiver in Figure 9-12. We choose an IF of20.46 MHz, a DAC sampling rate of fDAC = 81.84 MHz and implement a noiseGaussian generator with standard deviation of σ N = 24.292 .
The noise update ratewas kept constant at 1.023MHz (K N = 80 ) and the PRN code sequence amplitude, Avaried in steps of 0.5 from 1 to 16.5. The measured implementation loss is the sum ofRF cable loss and losses due to the conversion between the analogue and digitaldomain. After correcting for the implementation loss the estimated carrier to noise203Prototype receiver testing and resultscan be seen to precisely agree (0.21 dB r.m.s.) with the corresponding theoreticalvalues.Figure 9-12, Comparison of PIF receiver estimated and theoretical carrier to noise densities forBOC(1,1)The timing jitter of the DLL and SLL loops can be measured by subtracting theintegrated carrier phase measurement from the delay estimate from each loop.
Anarbitrary bias of carrier cycles must also be removed. An example of the timing jitterof the DLL and SLL loops is shown in Figure 9-13.204Prototype receiver testing and resultsFigure 9-13, Example timing jitter of DLL and SLL loopsThe DLL and SLL timing jitter were measured over a range of carrier to noisedensities.
Figure 9-14 shows a comparison of the receiver measured DLL and SLLtiming jitter with the theory given for a coherent BOC receiver given by Equation 4–20. Each point on the figure represents a dataset of 8-10 minutes taking readings at 1Hz. The receiver’s DLL and SLL correlator spacing were equal to a chip and a subchip respectively and both loop had loop bandwidths set to 1 Hz.205Prototype receiver testing and resultsFigure 9-14, Comparison of PIF receiver estimated and theoretical code tracking jitter forBOC(1,1)∆ DLL = TC , ∆ SLL = TS , BDLL = BSLL = 1 Hz .20610 Single chip GPS and Giove-A receiverIn this chapter we present a demonstration of terrestrial reception and processing ofPSK signals from the GPS satellites and the BOC(1,1) signal from the Giove-Asatellite.
This was achieved through a prototype FPGA-based GNSS receiver, whichwas developed as an extension of the PIF receiver. The architecture of this receiver isdescribed which combines the GNSS correlator and processor functions into an singlesystem-on-chip solution suitable for space applications. This design is intended toreplace the aging chipset in current SSTL SGR receivers.
This demonstrationprovides an illustration of the practical challenges faced in receiving Galileo signalsand implementing the BOC acquisition and tracking techniques developed during thisresearch.10.1 Single chip receiver overviewThe heart of any hardware GNSS receiver is its correlator and processor architecture.Currently most GNSS receivers use Application Specific Integrated Circuit (ASIC)chipsets to perform the operations required by the correlator and processor.
The massmarket of terrestrial GNSS receiver has fueled development into reducing the size andpower consumption of these chipsets, making a single chip baseband solutiondesirable. SSTL’s SGR receiver uses the Zarlink chipset, which provides a singlechip 12-channel receiver or two-chip 24-channel receiver. Similar chipsets such asthe SIRFstarIIA [SiRF 2005] provide a system-on-a-chip (SOC) 12-channel solution.Both these chipsets use a separate RF down-conversion stage, which can generallycompressed into a small low-power package.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
