Advanced global navigation satellite system receiver design (797918), страница 21
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This example uses theSSTL SGR receiver’s SNR filter and loss of lock threshold (3dB). The receiverdeclares loss of lock almost half a second after the actual dropout has occurred due tothe effect of the SNR filtering.Figure 6-14, Loss of lock from 15 dB SNR (SGR filter)A slip to an incorrect BOC tracking state cannot be reliably detected using the changein the receiver estimated SNR.
This is because the difference in peak amplitude fromthe central BOC peak to its adjacent peak can be as small as 0.75 dB for aBOC(6×fC, fC) modulation. This small variation in SNR takes a significant amount offiltering resulting in a long time to detect an invalid tracking state. In addition, a 0.75dB variation in SNR could easily occur through variations the receiver environment,multipath or antenna pattern under dynamics.Figure 6-15 provides an illustration of SNR estimation of a single sub-chip slip after a100ms signal outage.
After the outage the receiver locks onto an invalid timinglocation with only a small SNR difference (0.75 dB).141BOC tracking with double estimation receiverFigure 6-15, Example of receiver SNR estimation of a slip in trackingThe BJ algorithm provides a method by which a receiver can detect a false trackingcondition. However, the relative peak values also require a significant amount offiltering in order to make a correct decision in the presence of noise.
As shown inChapter 5.4 the BJ algorithm takes 303 ms to detect a slip in tracking for aBOC(2×fC, fC) modulation and 810 ms for a BOC(6×fC , fC) modulation. Hence, BOCreceivers using the BJ algorithm can be in a false lock condition for a significantamount of time before it can detect it.False lock in a BOC receiver causes significant errors in the receiver’s positionestimate. For example when attempting to receive a BOC(15, 2.5) modulated signal,false lock conditions can cause errors ranging from a minimum of 10 m to greaterthan 100 m in the worse case.
Therefore, the BJ algorithm is essentially an aposterioritest because it must maintain a false condition for an amount of time before detectionand potential correction of invalid tracking is possible. In our opinion the BJalgorithm is therefore unsafe for safety critical applications where the integrity of thereceiver’s tracking is of vital importance.The existence of two estimates of the received signal delay present in the DE BOCreceiver solves the problem of integrity in a BOC receiver.
There are no false lock orinvalid tracking states when operating the DE BOC receiver. The SLL settles to142BOC tracking with double estimation receiverinteger sub-chip offsets from the correct, valid delay estimate. The delay estimatederived from the DLL allows correction of the SLL delay estimate wherever the SLLhas settled to. Therefore, the DE BOC receiver corrected delay estimate, τˆ + isinstantaneously corrected for tracking slips of integer sub-chips and the integrity ofthe receiver is never compromised.6.7Hardware requirements of the DE BOC receiverThe simplicity of the DE BOC receiver architecture provides an attractive choice ofthe GNSS receiver designer.
The DE BOC receiver provides correlator architecturecompatible with the leading unambiguous BOC search technique with no changesrequired to the receiver hardware. By locking the sub-carrier delay estimate τˆ* to thecode estimate τˆ during search (i.e. aligned code and sub-carrier) the preferred SCCsearch technique can be implemented (see Section 5.3). All other proposed BOCtracking techniques will require additional hardware resources to become compatiblewith the SCC BOC search technique.The correlator hardware required for the leading BOC tracking techniques are shownin Table 6-5. The DE BOC receiver and BJ algorithm are both considerably moreefficient with a receiver’s hardware resource.
The DE receiver uses two additionalmultipliers and an additional local oscillator when compared to the BJ algorithm.However, the additional multipliers are one-bit and therefore the limiting factor indesigns will be the number of storage elements used (integrators). The DE receiveruses two less integrators per channel than the BJ algorithm and hence provides themost efficient use of hardware. An example of hardware resource utilization in aprototype DE BOC receiver is given in Section 8.4.143BOC tracking with double estimation receiverTable 6-5, Hardware requirements of BOC tracking techniquesReceiver typeMultipliersIntegratorsLocal oscillatorsLow pass filtersSSB2×Carrier,41×Carrier,24×CodeMGD (N=4)2×Carrier,1×Code1818×CodeBJ2×Carrier,6.82×Carrier,01×Code88×CodeDE1×Carrier,1×Carrier,01×Code61×Carrier,4×Sub-carrier,1×Sub-carrier,6×Code1×Code0Summary of the advantages of a DE BOC receiverAs detailed in this chapter the concept of independently tracking the incoming subcarrier and code provides a number of performance advantages over the BOC trackingschemes given in the literature.
These advantages can be summarized as follows. Rapid, smooth and reliable acquisition performance – The DE BOC receivercompletely removes the BOC ambiguity providing rapid acquisitionequivalent to that of a PSK receiver. Precise timing jitter – Combining independent delay estimates from its SLLand DLL the DE BOC receiver provides unambiguous BOC tracking withprecision equivalent to tracking using traditional early-late gates. In [Belloand Fante 2005] the BJ algorithm [Fine and Wilson 1999] is shown to be theonly other BOC tracking technique which results in no degradation of trackingjitter from early-late gates.
No integrity issues – The DE BOC receiver provides unambiguous BOCtracking without relying on a peak detection (BJ algorithm) which requirescareful threshold tuning. This provides a more robust design which can easilybe corrected for distortions (asymmetry) in the transmitted signal. Automatic slip correction – The DE BOC receiver maintains a valid delayestimate for any sub-chip offset within the correlation interval.
This removesthe risk of maintaining a false-lock condition for a significant period beforecorrection.144BOC tracking with double estimation receiver Lowest hardware utilization – The DE BOC receiver provides the mostefficient use of hardware resources compared to other unambiguous BOCtracking techniques.1457GNSS signal generators and the Giove-A satelliteIn this chapter we discuss hardware implementations of GNSS signal generators. Themission and payload of the Giove-A satellite is summarised with emphasis given tothe SSTL built Galileo signal generator that this research has contributed towards.The design of a prototype IF GNSS signal generator is then detailed.
Stemming fromthe original SSTL design, this signal generator has the added capability ofsynthesizing additive noise to the IF signal. These signal generators will be used todemonstrate and evaluate receiver performance in Chapter 9. The receiver testingusing the Galileo signals from the Giove-A satellite is described in Chapter 10.7.1The Giove-A mission and payloadOn the 11 July 2003 SSTL was awarded a 28 million euro contract to construct thefirst Galileo test-bed satellite Giove-A. The Giove-A satellite was successfullylaunched on the 28th of December 2005 from the Baikonur Cosmodrome inKazakhstan, via a Starsem Soyuz-Fregat rocket (see Figure 7-1).
Giove-A is the firstSSTL mission outside low earth orbit (LEO) and was placed in a high-radiationenvironment at 24,000 km altitude with a 14-hour orbit. The satellite weighs in at 660kg is 3-axis stabilisation and dimensions of 1.3 m (height) × 1.8 m (width) × 1.65 m(depth). Two sun-tracking solar arrays each 1.74 m long provide 700 Watts ofelectrical power to the payload.The primary mission objectives of Giove-A were to secure the Galileo frequencyfilings and validate key technologies for the final Galileo constellation.
The satellitecarries an environmental payload to measure the radiation and spacecraft chargingexperienced in the Galileo orbit. Also on-board is a experimental GPS receivermanufactured by SSTL to demonstrate operation outside the GPS constellation.146GNSS signal generators and the Giove-A satellitea)b)Figure 7-1, Giove-A satellite: a) at ESA for environmental testing b) on the launch padThe payload of the Giove-A satellite is shown in Figure 7-2.
The primary payload isa fully space qualified signal generator commissioned by ESA. Driven by one of tworubidium atomic clocks this payload is capable of producing representative Galileosignals in three frequency bands (E1, E5, E6) although only two bands may betransmitted at any particular time. The space-qualified units were sourced by ESAand are referred to as ‘customer furnished items’ (CFI). In order to remove theschedule risk of the CFI Galileo signal generator, SSTL supplied a backup Galileosignal generator based on commercial of-the-self (COTS) components. Thisdevelopment consists of the navigational message generation unit (NMGU) and themodulator, frequency generator and up-converter unit (MFUU).
Both units are drivenby a 10.23MHz reference derived from the atomic clocks.The NMGU controls the synchronised start of signal transmission with Galileo timeand provides the navigational message data for all signals being transmitted. TheMFUU generates representative Galileo spreading codes and sub-carrier modulations(BOC) synchronised with the incoming navigational data and up-converts the signalto RF. The MFUU is capable of producing representative Galileo signals in threefrequency bands (E1, E5, E6), although only two bands may be transmitted at anyparticular time.147GNSS signal generators and the Giove-A satelliteFigure 7-2, Baseline payload design for Giove-A [Falcone et al 2006]The MFUU consists of a modulator and two up-converter units, shown in Figure 7-3.The modulator consists of a single radiation tolerant Actel RT54SX72S fieldprogrammable gate array (FPGA) and two Analog Devices AD9755 digital-to-analogconverters (DAC), which were radiation tested.
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