Roland A. - PVD for microelectronics (779636), страница 61
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As a result, extra Si is often blended into the target during its manufacture to allow the user some flexibility in film stoichiometry.For example, a WSi x film with x = 2.0 to 2.5 might be produced by PVDfrom a given WSi2.7 target, depending on process conditions and postdeposition sintering.
Since the as-deposited silicides tend to be amorphous, ahigh-temperature post-PVD sintering step (e.g., 900-1000~is often usedto increase and homogenize grain size so that low-resistivity polycrystalline films can be obtained that, depending on the specific silicide and itsstoichiometry, are in the range of about 30-100/xD,-cm.9.7.2T I S I 2 AND C o S I 2These material systems are selected to illustrate the use of metal sputteringfollowed by annealing for silicidation. For example, PVD Ti is widely usedat the Si contact level as a chemical cleaning agent to reduce native siliconoxide.
After annealing, this same Ti film reacts with and consumes Si toform a low-resistance TiSi 2 layer of much greater thickness ( ~ 2.7 timesthicker) than the starting Ti film. The amount of Si consumed during Tisilicidation must not be so great that it affects the junction (which can bequite shallow ( < 100 nm) in advanced ULSI devices), and as a result TiSi 2layers are typically < 40-nm thick for this application with even thinner Tistarting thickness ( < 15 nm). Also, since a 1-~ change in Ti thickness results in a 2.7-A change in TiSi 2 thickness, excellent control of startingPVD Ti film thickness is required for process repeatability.Both Ti and Co are well suited for the salicide process in which the elemental metal is sputter deposited as a blanket film and then processed to330R.
POWELL AND S. M. ROSSNAGELselectively leave a low resistivity film of TiSi 2 or CoSi 2 on oxide-definedwindows [9.43]. Although salicide processing with Ti is established in present VLSI devices, a future concern is that the TiSi 2 formed after lowtemperature annealing ( < 600~has the C49 phase with base-centeredorthorhombic crystal structure and relatively high resistivity ( ~ 60-70/xl~cm). Therefore, a second anneal at higher temperature ( > 700~is required to transform the C49 phase into the desired C54 phase with facecentered orthorhombic crystal structure and low resistivity ( ~ 15-20/xf~-cm).
While this has not ruled out Ti-salicide processing for VLSI devices, the C49-to-C54 transition temperature increases with decreasing linewidth, and the higher temperatures may not be compatible with the reducedthermal budget of ULSI devices. Also, scaling down of the TiSi 2 layer thickness further increases the transformation temperature and/or annealing time.As a result, increasing attention is being given to Co-salicide processing.Although Co offers a number of potential benefits [9.43], its applicationin multilevel metal interconnection is relatively new and poses some interesting challenges.
First of all, care must be taken when using PVD Co forIC processing, since it is a midgap trap in Si and will affect MOS properties if it is allowed to cross-contaminate processing equipment. The othermajor issue relates to Co being a ferromagnetic material with high magnetic permeability. To efficiently sputter such a material with a magnetron,the ferromagnetic target must not shunt the magnetron cathode's plasmaenhancing DC magnetic field or act as a magnetic pole piece of the source.Even if sufficient electron confinement can be obtained in the presence ofthe target to sustain a magnetron discharge, the magnetic field perturbationmay alter the desired target erosion profile with adverse impact on targetutilization and film uniformity.
Therefore, a magnetron with very strongpermanent magnets and/or a very thin target must be used to ensure that thetarget material is magnetically saturated. Although very thin targets aregenerally at odds with high target life, the amount of Co needed for this application is sufficiently small (tens of angstroms per deposition) that ratherthin Co targets can be used. In this regard, target suppliers have begun tofabricate Co targets with smaller grains and more preferred orientation.This microstructural engineering serves to reduce the relative permeabilityof the target and increase the pass-through flux of magnetic field for agiven target thickness.
Finally, the basic PVD source technology has already been developed to deposit cobalt alloys for hard disk drives (e.g.,CoCrTa, CNiCrTa, and CoCrPt), although advanced magnetic hard disksare much smaller in diameter (<- 3 inch) than production Si wafers. Otherthan the case of Co, however, sputtering of magnetic materials is rarely attempted in semiconductor processing.PVD MATERIALS AND PROCESSES33 1While the ferromagnetic nature of Co makes it more difficult to sputterthan Ti, Co offers a number of process advantages over Ti, including theability to deposit epitaxiaI CoSi, on Si(IO0).
Ironically, PVD Ti has playedan enabling role in this process, which uses an ultrathin intermediate layerof Ti (1-5 nm) sandwiched between a thicker Co film (15-20 nm) and theSi substrate [9.44].The Ti cleans the native oxide from the Si surface and,during subsequent annealing in N,, moderates the diffusion rate of Co tothe Si leading to the growth of a single epitaxial CoSi, phase as opposedto a mixture of polycrystalline CoSi and CoSi, phases.-~ollowingannealing, a TiN/CoSi,/Si(lOO) structure is formed. The process requires gooduniformity of ulirathin Ti films and suggests that PVD Ti will continue toplay an important role in silicide formation, even though the silicide beingformed is CoSi,.9.8 Copper9.8.1 METALLURGICALISSUES FOR PVDPVD of Cu is well established in multilevel metallization.
For example,sputtered Cu is sometimes used as part of the back-end-of-line metallization process for chip assembly and packaging. Also, alloy targets of Alwith a few percent of Cu (e.g..AI-Cu. Al-Si-Cu) are commonly used to deposit interconnect wiring, and even though the Cu is alloyed with A1 in thetarget matrix, the sputter process results in a flux of elemental Cu atoms atthe substrate.
On the other hand, serious interest in using pure copper interconnects as a material replacement for AI and its alloys is a relativelynew development.I n particular, Cu has lower intrinsic resistivity than AI (1.7 p a - c m at20°C vs = 3 p a - c m for Al alloys) that should enable higher-speed, deepsubmicron devices ( I0.18 pm) through reduced RC time-constant delaysas well as greatly reduce the number of metal levels required to route thewiring of an advanced microprocessor (Fig. 9.33). Cu also has a highermelting point than Al and a better thermal expansion match to that of SiO,(linear coefficients of expansion for Al, Cu, and SiO, are = 23.6, 16.5, and0.5 ppm per " C , respectively), leading to superior resistance to stress migration, hillock formation, and electromigration - although both Cu andA1 exhibit their best electromigration resistance when they are stronglytextured in the ( I 1 I ) direction.The primary clock-speed advantage of using Cu over A1 is derivedfrom its lower resistivity and is achieved by introducing Cu at the upper332R.
POWELL AND S. M. ROSSNAGELinterconnect levels, where conductor lengths can be of the same order asthe chip size. On the other hand, the increased reliability advantage of Cuover A1 is realized by introducing Cu at the lower interconnect levelswhere the current density in the fine lines can be large enough to induceelectromigration failure in traditional Al-based interconnects. In order totake advantage of Cu for upper or lower-level interconnect applications,integration issues such as oxidation (Cu does not form a self-passivatingoxide like A1), corrosion, and poor adhesion to oxide need to be resolved.Also, suitable diffusion barriers need to be developed to prevent the rapidmovement of Cu into both SiO 2 and Si. For example, Cu migration intoSiO 2 can create electrical leakage paths between adjacent metal linesand/or layers.
Also, Cu forms deep-level traps in Si and can consume Sivia formation of Cu3Si at temperatures as low as 200~ Fortunately forPVD, candidate barriers for Cu such as Ta and TaN can be deposited withrather good conformality by sputtering.In addition, a commercially viable anisotropic plasma etch process forCu has been notoriously difficult to develop because the vapor pressure ofCu halides are very low at room temperature.
This means that one cannotuse the conventional "subtractive" process for MLM in which a blanketPVD metal film is deposited over a planarized oxide and then patternedand etched into separate metal lines by reactive ion etching (RIE). As discussed in Chapter 6, the industry is expected to switch to a damascene typeof patterning (Fig. 9.32) in which Cu is first deposited into trenches thatwere first etched into the dielectric and is subsequently planarized, e.g., bychemical-mechanical polishing (CMP). As a further refinement, dual-damascene wiring can be used in which both vias and trenches are first etchedinto the dielectric and then are filled with Cu in the same deposition step[9.451. This will be a particularly challenging application for PVD (analogous to simultaneously filling a rain gutter and a down spout) and willhave to be carried out at low process temperatures consistent with the organic dielectrics being considered for < 0.18-/zm devices.
In addition, filling must be done without leaving buried voids or forming seams where thesidewall deposits meet. The risk is that such features could be exposedafter the Cu is chemomechanically polished back, producing topographicalsurface defects.Whether or not PVD is up to the challenge of dual-damascene Cuwiring, it is worth noting that other candidate Cu deposition methods suchas CVD Cu and electroplating may require either a PVD barrier/adhesionlayer (e.g., PVD Ta or TaN) and/or a PVD Cu seed/nucleation layer.
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