Roland A. - PVD for microelectronics (779636), страница 65
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This is analogous to the RC time constantdelay introduced by a multilevei metal interconnect stack due to capacitivecoupting between adjacent metal lines in a given level.Based on such concerns. IC industry roadmaps show a trend away fromwirebonded leads and toward flip chip packaging technology in which thefull area of the chip is directly attached to the package [9.60]. In mostflip-chip applications, the wire bonds are replaced by small metallicbumps on the circuit side of the die. The connections from die to substrateare then made by flipping the chip circuit-side down onto the bondingpads and ref owing the underlying bump metallization.
Flip chip technology has been used in microelectronic production for many years: however, its increased use in advanced packaging affords a market opportunity for PVD. For example. workers have reported 19.611 that PVD is anattractive way of forming a popular. under bump metallurgy (UBM) thatis typically carried out in a batch mode using sequential e-beam evaporation of a chromium underlayer (Cr). a chromium-copper interlayer, and aCu overcoat layer. Using an S-GunThf sputter source with two independently powered.
ring cathodes - one made of Cr and the other made ofCu - it was possible to deposit the same CrICr-Cu/Cu stack within a single PVD module on a cluster tool. As with the e-beam evaporated stack,the PVD stack was a seamless structure without any interface evident between the layers.PVD MATERIALS AND PROCESSES349References9.1 B. Roberts, A. Harrus and R.
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