Roland A. - PVD for microelectronics (779636), страница 64
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M. ROSSNACELshows that a uniformly thick. conformal PVD layer in a hole of aspect ratiohlw+>> 1 will at best have step coverage = 1/(2 hln~),which is 10% for a5:l aspect ratio hole. One solution is to utilize a hot PVD process such asreflow A1 in which materia1 from the adjacent field is moved into the holeby surface diffusion, the field itself being simultaneously planarized.Another approach is to abandon PVD for this application in favor of a surface-activated CVD process.As a consequence of the relatively high CVD pressure (= 0.1-10 Torr istypical for C V D metal deposition) and chemistry used, both the mean freepath of the precursor molecules and their sticking coefficients are often reduced relative to that of the sputtered atoms in PVD.
As a result, the precursor molecules undergo a large number of collisions both in the reactorand with the surfaces of microstructures on the wafer, which. coupled withsurface diffusion and the proper process conditions, can give highly conformal films with uniform thickness and .= 100% step coverage. Thismode of deposition is also well suited to rapid filling of narrow, high aspect ratio features since it requires only that deposited film thickness begreater than one-half of the via width - more o r less independent of thevia height. For example, a I-pm-deep X 0.18-pni-wide via could be filledby depositing a fully conformal 113 x (0.18 p m ) = 0.09-pm-thick film.Finally.
C V D is sometimes capable of coating even reentrant feature5 - afeat that is not possible with a more line-of-sight method o f depositionsuchPVD.The term r . o t ~ f i ~ r r ~ rist t lused in different u.;~ysin the litertuture and relates tohow unifor~nlya nonplanar structure is coated with a thin film. With respectt o u contact. via, o r trench. 3 conf'or~iialfilm is one whose \idewall coverugeis of uniform thickness and equal 10 its boitom coveruge.
In general. thisthickness will he less than the ~hicknes\on the field. A conuormal film whosethicknchs is cqual to the thickness deposited on the field is said to he "fullycont'ormal" or to have "100% step coveruge."In spite of its compatibility with steep topography. C V D metallizationhas its own set of challenges. For example. it has been difficult to developappropriate CVD chemistries to deposit high-purity Ti, Cu-doped A1 alloys, or TiN films having both high conformality and purity comparable toPVD TIN.
Also, when ultrahigh aspect ratio topography is not an issue(e.g., deposition of 1 p m of slab A1 on a planarized oxide), PVD offers amature and highly cost-effective solution. There are. however. situations inwhich the complementary benefits of each method can be used to advan-PVD MATERIALS AND PROCESSES345tage m e.g., the well-established use of PVD Ti/TiN as a contact-barrierlayer-adhesion liner for CVD W contacts and plugs.As shown schematically in Fig. 9.40, there are many other possibilitiesfor combining CVD and PVD in the future.
For example, Cu-doped CVDA1 via plugs (AR = 5:1, 0.25/~m) have been produced by partially fillingthe via with undoped CVD A1 and then, without a vacuum break, depositing a PVD A1-Cu(1%) overlayer [9.57, 9.58]. A brief anneal (e.g., 30 secat 300~was then used to diffuse the Cu from the PVD film uniformlythroughout the filled via. When a vacuum break was used between theCVD A1 and PVD A1-Cu deposition, an amorphous interfacial layer formedFIG. 9.40Illustration of selected processes combining PVD and CVD.346R. POWELL AND S. M. ROSSNAGELthat acted as a diffusion barrier to subsequent Cu diffusion.
This in turn necessitated a much higher thermal budget anneal to diffuse the Cu (30 minat 450~Hence, a vacuum-integrated cluster tool is required to optimizethe process.Other PVD/CVD combinations that are under active development include the use of an RF-ionized PVD Ti layer combined with a CVD TiNbarrier, and the use of a PVD Cu/Ta bilayer to facilitate subsequent fillingwith Cu by CVD or electroplating.
Also, the cold-hot PVD A1 processmight be improved by use of a more conformal A1 seed layer deposited byCVD A1 or directional, ionized PVD A| with sufficient resputtering to satisfy sidewall coverage requirements. Finally, we mention a novel CVDPVD approach to A1 plug fill - - known as polysilicon-aluminum substitution ( P A S ) - that relies on the same thermodynamic driving force thatcauses AI junction spiking [9.59]. In its simplest form, the PAS process involves filling of an oxide via with CVD poly-Si, removal of the poly-Si onthe field regions by chemomechanical polishing, and then blanket deposition of PVD AI. A lengthy anneal of the vias (e.g., 500~ for 3 hours) allows the poly-Si to diffuse up into the bulk of the A1 and the AI to diffusedown into the via where it substitutes for the poly-Si.
Unlike the departedsilicon, however, the AI in the via after annealing is single crystal. Doneproperly, PAS has been shown capable of filling 0.18-/~m, 10:1 aspect ratiovias with single-crystal AI.Assuming that such hybrid process flows are cost-effective, the majorconcern is how to avoid cross-contamination when PVD and CVD aredone on the same vacuum-integrated process tool, given the high CVD operating pressures ( ~ 1-10 Torr for CVD vs 1 mTorr for PVD) and the exotic organometallic precursors that are likely to be used m such as DMAH(dimethyl-aluminum hydride) for AI, Cu(II)-(hfac) 2 for Cu (hfac is the ligand l , l , l , 5 , 5 , 5 - h e x a f l u o r o - a c e t y l - a c e t o n a t o ) , and TDMAT (tetrakisdimethyl-amido-Ti) or TDEAT (tetrakis-diethyl-amido-Ti) for TiN.
Theuse of such chemistry on a P V D - C V D cluster tool is a particular concernfor hot PVD A1 steps that are highly sensitive to even trace amounts of oxidants and hydrocarbon contamination, and will require good vacuumbuffering and possibly multiple pump/purge cycles of the CVD module(e.g., pump to 10 - 6 Torr + backfill with Ar to 1 Torr + pump-down)to reduce the precursor partial pressure below a critical level before opening theisolation valve to the central handler.Finally, we note that cost-of-ownership applies equally to both PVD andCVD technology. However, in the case of CVD the additional cost ofpumps and maintenance to deal with reactive and/or corrosive gases andeffluents needs to be considered.
Also, cost and availability of the precur-PVD MATERIALS AND PROCESSES347sor can be an issue. For example, although CVD W plugs are widely usedtoday (3H 2 + WF 6 = W + 6HF), the low availability and high cost of suitably pure tungsten hexafluoride (WF6) in the 1980s delayed widespreaddeployment of both CVD W and WSi 2 by many years.
In this regard, it isinstructive to estimate chemical cost associated with the A1 sources inPVD A1 and CVD A1. The cost of the relatively common organometallicDMAH = (CH3)z-A1-H used in CVD A1 is about $25/gm (in 1997 dollars).Since the weight of a 1-~m film of A1 (p = 2.7 gm/cm 3) deposited over a200-mm wafer is about 0.08 gm, the cost per wafer associated with this A1precursor is ~ $2.10 ~ assuming that the CVD process is 100% efficientat converting the gaseous precursor into solid-phase A1 films. In practice,the utilization efficiency is less than 100%, and a large fraction of the precursor ends up being pumped out of the chamber.
Hence the actual cost perwafer could be several times greater ~ e.g., $5-10. By comparison, thecost of a high-purity A1 target is about $5000 and produces about 80001-/~m AI films over target lifea cost of ~ $ 0.65 per wafer.9.10 Upper-Level MetallizationThe topmost layer(s) of metal interconnection in a multilevel stack is typically reserved for power distribution and the transmission of global signals that run the length of the chip.
To minimize voltage drops over theselong runs, the wiring usually has large cross-sectional area Ae.g., verythick lines with very wide p i t c h - which reduces the resistance per unitlength: R / L = p / A . The top layer of metal also provides the large-areabonding pads that are used to connect the chip to the outside world. PVDmetal films between the bonding pad and the bonding wires can then serveas diffusion barriers, promote adhesion, and/or provide a better thermal expansion match to the wire bonding metallurgy. For example, in the socalled bump fabrication method used with tape automated bonding (TAB),an AI alloy bonding pad might be coated with a bilayer of PVD Au on PVDTiW.
The TiW serves as a diffusion barrier between the Au and AI, and theAu provides an adherent surface for a subsequent electroplated bump ofmetallic Au. PVD is also used for backside conductive coating of the chip.For example, a PVD gold or Pt film might be deposited onto the backsideof the Si. For this application, care must be taken in the design of the waferholder and shielding to prevent any metal contamination from reaching thewafer frontside since metals such as Au diffuse rapidly in Si and can reduce minority carrier lifetime.
Gold is extensively used in GaAs-based ICsand actually has a lower resistivity than A1 ( ~ 2.2/zl-l-cm). However, high348R. POWELL AND S . M. ROSSNAGELdiffusion coefficients in both Si and SiO, and poor adherence to oxide havediscouraged its use as an interconnect in silicon microelectronics.found in the individual chips, circuit boards, and connectors. This corresponds to about 0.01 oz of Au in a 20-lb computer, which pound-for-pound isthree times the amount of gold in the average gold mine ( 1 ton of ore yieldsabout 0.3 oz of Au).The requirements of advanced high-speed chips such as microprocessorsand telecommunications devices are driving IC packaging to smaller sizesand larger numbers of input/output (I/O) connections.
The establishedmethod of packaging VLSl devices is to wire bond connections from thedie to a leadframe; however, this method is less attractive for advancedULSI chips due to the cost and performance of a densely-packed, wirebonded assembly. For example, cross-talk between adjacent, closelyspaced wire bonds could degrade the intrinsic signal propagation speed expected from a high-speed chip.
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