Roland A. - PVD for microelectronics (779636), страница 5
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Figure 1.5 shows that, on anindustry-wide scale, the vast majority of PVD equipment in microelectronic production is used to deposit AI alloys (A| with ~ 1% of Si and/orCu), Ti, or TiN. This is followed by relatively low utilization of Ti-W alloys and refractory metal silicides such as WSi x and M o S i . As MLM technology evolves, it is likely that Cu interconnects and Cu-compatible barriers such as Ta and TaN will also join the most-favored PVD materials list.However, the Cu interconnect may be deposited using PVD in combinationwith other deposition methods - - e.g., a PVD Cu adhesion-seed layer followed by CVD Cu, or a PVD Cu "strike layer" followed by electroplatedCu (see Chapter 9).FIG. 1.5 Histogram showing the industry-wide use of PVD by film type.
Whereas many differentkinds of conducting films are deposited by PVD for advanced microelectronic applications, the dominant films are AI alloys, Ti, and TiN.INTRODUCTION11Thinking geometrically (see Fig. 1.6) one can regard PVD as havingfour major applications of interest in microelectronics: (1) a coating on thebottom of a contact hole, via hole, or trench; (2) a lining on the sides; (3)a plug that fills such a feature; and (4) a planar two-dimensional film.
Ablanket, conformal coating might simultaneously satisfy applications (1)and (2) and, if thick enough, (3) and (4) as well. The challenge for PVD isto cost-effectively deposit such films in features that have smaller dimensions and higher aspect ratios and to do this uniformly over larger-diameterwafers with film properties needed for advanced Si devices.In this regard it is worth pointing out that while PVD has achieved adominant position in microelectronic metallization, there are concerns thatthe step coverage of PVD films may not be good enough to conformallycoat and/or fill high aspect ratio features (AR -----4:1) in advanced ULSI devices (minimum feature size -< 0.25/J,m). The fundamental reason for concern is that the material ejected from a sputter target has a broad angulardistribution that results in a nonnegligible flux of low-angle material hitting the wafer surface.
The deposited film associated with this flux canshadow the high-angle material that would otherwise coat the sidewallsand bottom of the feature.The general situation is illustrated in Fig. 1.7, which shows how, for asufficiently steep feature and/or thick deposition, PVD films can preferentially build up material at the top of the feature. Sometimes referred toas an overburden or bread-loafing, this material can reduce bottom coverage, thereby preventing uniform coating of the sidewalls. If the PVDfilm is thick enough, this overburden can bridge the diameter of the holewith metal and lead to an undesired keyhole-shaped void being producedFIG. 1.6 PVD applications can be divided geometrically into those requiring a two-dimensional planar film and those requiring coating and/or filling of a three-dimensional feature.R.
POWELL AND S. M. ROSSNAGELHighAngleMaterial~/~~~LowAngleMaterialBuild\~1 Sidewalli c~BottomCoverageFIG. 1.7 A relatively large flux of low-angle deposition during conventional PVD can lead to preferential buildup of material at the upper edge of fine-geometry structures. This in turn limits bottomand sidewall coverage of thin films and may prevent void-free filling of the structure.within the volume of an otherwise filled plug. The future role of PVD inmicroelectronics will be influenced strongly by our ability to control thedirectionality of the deposition and to improve the step coverage of the resulting films. Chapters 6-8 will treat this important topic in detail, discussing a number of recent developments in PVD source technology andprocessing.1.2 PVD and the Interconnect RoadmapIt is almost obligatory in books about semiconductor technology to showthe evolution of device complexity by plotting such things as minimumfeature size, level of integration, die size, and clock speed versus year.
Oneof the best-known and best-cited roadmaps is the Semiconductor Industry Association's National Technology Roadmap, referred to as the SIARoadmap, which in 1994 extended historic device technology trends out to2010 and identified device-driven and productivity-driven needs for keytechnologies such as interconnection that directly impact PVD. An updatedversion of the SIA Roadmap was released in 1997, which extended the industry's vision of the future through the year 2012 when, if the roadmap isfollowed, logic circuits will have minimum feature size of 0.035 /xm,memory chips will hold 256 gigabits of memory, and silicon wafers willINTRODUCTION13measure 450 m m in diameter.
In addition to extending the 1994 roadmapby two years and one process generation, the 1997 SIA roadmap added anew "technology node" at 0.15/xm, between the 0 . 1 8 / x m and 0 . 1 3 / x m device generations on the earlier roadmap.Because microelectronics is digital, the letter "K" used to indicate bit countper chip (e.g., a 256K DRAM = 256 kilobits) does not equal 1000 as in themetric system. Instead, the microelectronic K has a value of 1024 = 2 j~which is very close to 1000 = 1 0 3. Knowing that 2 j~ ~ 1 0 3 and taking thelogarithm of both sides is also an easy way to remember that log~02 ~ 0.3.It is well beyond the scope of this book to present a comprehensive PVDroadmap (the reader is encouraged to review the actual SIA Roadmap orsummarized versions [1.6]).
Instead, in Figs. 1.8-1.10 we present greatlyabbreviated roadmaps in graphical and tabular form based on both the SIARoadmap and others (e.g., those generated by SEMATECH and theSemiconductor Research Corporation (SRC)) to set the stage for laterchapters on PVD process and hardware development. Two caveats need tobe made regarding technology roadmaps in general. The first is that aroadmap can extrapolate historic trends but cannot anticipate truly breakthrough technology. The second is that device details such as aspect ratioand number of metal levels are company-specific, so that a range of valuesFIG.
1.8(a)R. POWELLAND S. M. ROSSNAGELFIG. 1.8 Evolution of silicon device technology showing (a) decreasing feature size, (b) increasingdie area, and (c) increasing complexity over time (Fig. 1.8c from ref. 1.7).INTRODUCTION15FIG. 1.9 Evolution of silicon IC sophistication is illustrated with product generations of Intel microprocessors (courtesy of VLSI Research Inc.).is more appropriate for a given attribute at a given time. Nevertheless, several observations related to the application of PVD in microelectronics canbe drawn from Figs.
1.8-1.10.By 2001, when the geometry of devices in pilot production is 0.18/~m(equivalent to a 1-Gigabit = l-Gb level of integration in a DRAM),leading-edge wafers will be 300 mm (12 inch) in diameter. Thus, not onlywill device geometry be smaller, but the area on which PVD films are to bedeposited uniformly will be over 2 times greater than for a 200-mm wafer.Of special note is that the aspect ratio of features to be coated and/or filledwith metal could become so high for both memory and logic that it will exceed the step coverage capability of PVD. The reason for the rise of aspectratio is that vertical device scaling has not kept pace with lateral scaling. Inparticular, given the relatively high dielectric constant of the CVD oxides(k ~ 4) used for ILD, it is difficult to bring advanced metal interconnectlevels closer than about 0.8/.Lm without increasing parasitic capacitance tothe extent that signal propagation is seriously delayed.
Therefore, when adevice designer shrinks a via hole diameter, the aspect ratio is likely to goup since the vertical distance between metal-(n) and metal-(n + 1) cannotgo down. The development of lower-k dielectric interlayers (e.g., k = 2)R. POWELL AND S. M. ROSSNAGELY e a r of FirstProduct S h i p m e n t1997complexity (DRAM)Transistor- minimum feature size- gate oxide equivalent thicknessjunction depth at channel9Ch,p S,z. (.o,.ge)- DRAM1999Wafer Diameter (mm)20031 Gbit1 Gbit4 Gbit0.25 lain4-5 nm50-100 nm0.18 lain3-4 nm36-72 nm0.15 Ixrn2-3 nm30-60 nm0.13 pm2-3 nm26-52 nmF280 mm 2300 mm 2- microprocessor2001256 Mbil.! 400 mm 2340 mm 2200 mm(8 inch)200 & 300 mm(8 &12 inch).445 mm 2385 mm 2560 mm 2430 mm 2300 mm(12 inch)300 mm(12 inch)Number of Metal LevelsI:- memory (DRAM)- logic (microprocessor)I 2-36,~Contact/Via Aspect Ratio- memory-Iogm36-7.5.5"12.2:137.= 6.3:1! 2.2:17.0:12.4:17.5:12.5:1Maximum Interconnect Lengthfor Logic (meters/chip)8201,4802,1602,840Particles-critical size- allowed padicle densitygreater than s=ze(per m2)125 nm12590 nm125i 75 nm12565 nm125FIG.
1.10Technology R o a d m a p for Interconnect, based on the SIA National Technology Roadmap[1.6].could help slow the growth of aspect ratio, but the approach is limited bythe fact that the lowest dielectric constant "material" is free space with a dielectric constant of k = 1.The trend for both memory (e.g., DRAMs) and logic devices (e.g., microprocessors) is clearly toward increased levels of MLM interconnect (sixor more levels for logic), and since each level requires one or more engineered metal depositions, this trend also supports the continued growth ofPVD.
It should be noted that although a logic and a memory chip may beat the same device generation, the level of integration can be quite different. For example, a 256M DRAM chip and a microprocessor might bothrequire the same 0.25-/xm minimum feature size, but the microprocessormight have 10 times fewer transistors. The severe limits put on particlesand other foreign matter by continued shrinking of minimum feature sizeand continued growth of die area will require PVD tools to provide thehighest levels of vacuum, robotic, and process cleanliness. Finally, itshould be underscored that the economic and support issues related to PVDequipment (cost-of-ownership, tool up-time, mean-time-to-repair the tool,INTRODUCTION17etc.) will be every bit as important as the technical quality of the PVDprocess (blanket film properties, step coverage over high aspect ratio features, within-wafer uniformity, etc.).1.3 Additional Sources of Information on PVDNeither this book nor the references given at the end of each chapter areintended to be a comprehensive review of PVD for microelectronic applications.
Fortunately, there are a number of ways of obtaining additional information about PVD process and hardware technology and of keepingabreast of developments in this fast-moving field.Other than this volume, we are not aware of any monograph on the useof PVD in modern microelectronics. The book Physical Vapor Deposition[ 1.8] presents a good overview of the use of both e-beam evaporation andsputtering in industrial coating circa 1985, and useful review chapters onsputter deposition relevant to semiconductor fabrication can be found inhandbooks such as Thin Film Processes [ 1.9, 1.10], Thin Film Processes H[ 1.11, 1.12], the Handbook of Thin Film Process Technology [ 1.13 ], and inthe series on VLSI Electronics: Microstructure Science [ 1.14].
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