Roland A. - PVD for microelectronics (779636), страница 4
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Although insulating films can bedeposited by RF magnetron sputtering, methods such as chemical vapordeposition (CVD) and spin-on glass (SOG) technology dominate thedeposition of the insulators that electrically isolate one level of metallization from the next and one metal line from an adjacent one on the samelevel.Figure 1.3 presents a simplified cross section of an advanced IC and isintended to illustrate how PVD films are utilized for microelectronic fabrication.
After the individual transistors are fabricated within the siliconsurface, they are contacted and wired together locally to form specificfunctions (memory cells, logic gates, etc.) and then interconnected together globally to form a fully functioning integrated circuit on a chip.
Thenumber of front-end-of-line (FEOL) process steps needed to form activestructures as compared to the number of back-end-of-line (BEOL) processsteps needed to connect them has steadily decreased. In fact, it has been estimated that fully 60% of the process steps in making an advanced microprocessor are devoted to interconnection [ 1.2].The reason for the dominance of BEOL can be understood from devicescaling theory [1.3].
As the minimum feature size of a device is reduced toFIG. 1.3 Simplified cross section of an advanced IC (Intel Pentium chip) showing how PVD filmsare utilized. The IC shown uses CVD W plugs; however, device roadmaps show the eventual replacement of W by A1 and/or Cu.R. P O W E L L A N D S. M. R O S S N A G E Lobtain increased device speed and device density, scaling theory showsthat the cross-sectional area of the interconnect line needs to be decreasedand its length increased.
By the year 2001, the total length of interconnectson an advanced microprocessor may well exceed 2 km. A major designchallenge has therefore become routing the lengthened interconnect linesso as to minimize RC time-constant signal propagation delays caused bytheir parasitic capacitance (C) and ohmic resistance (R). Interconnectdelay is of increasing concern for advanced ultralarge scale integrated(ULSI) devices because even a small RC time delay associated with thedense wiring (e.g., pitch between adjacent lines < 0.5/xm) can be a largefraction of the intrinsic clock cycle time (e.g., a 1 GHz frequency clock hasa cycle time ~ 5 nsec), which in turn limits the high-speed performancethat was built into the chip.
The device packing density of advanced ICshas become so large (e.g., ~ 107 transistors per cm 2 in a 64Mb DRAM) infact that the area needed to sensibly route the interconnects now exceedsthat of the Si chip itself.To deal with this situation, a high-rise architecture is used in which multiple levels of metal are isolated by and interconnected through multiplelevels of dielectric.
Analogous to the framing of a house, this multilevelmetallization (MLM) interconnect scheme results in a kind of "joist andstud" configuration with horizontal metal joists of rectangular cross section (the lines) connected by vertical metal studs with circular cross section (the contacts and vias). The chip area, A, required for multilevelwiring has been shown to depend on the number of levels, n, through theexpression [1.4]A !/2 = (PGm)( 1.1 )nwhere P is the pitch of the metal wires, G is the number of transistor gatesto be connected, and m is analytically determined to be ~ 0.2 for highdensity wiring designs. Therefore, all things being equal, adding an extralevel of metal to a three-level metal interconnect (i.e., increasing n from3 to 4) is equivalent to increasing the chip area by a factor of (4/3) 2 ~ 2.Regarding MLM nomenclature and terminology, the contact hole is theopening that connects the first level of metal (metal 1 or M1) to the Si device.
Via holes, on the other hand, connect one layer of metal to the nextthrough an interlevel or interlayer dielectric ( I L D ) ~ not to be confusedwith an intermetal dielectric (IMD), which is the insulator between adjacent metal lines in the same layer. ILDs are numbered as follows: The dielectric between the Si and M1 is referred to as ILD0, the dielectric between M I and M2 is ILDI, etc. This nomenclature is followed up until theINTRODUCTION7topmost layer of dielectric, which is referred to as the passivating layerand whose purpose is to provide physical and chemical protection of theunderlying metal and device structures during final assembly of the chipand to prevent the diffusion of moisture and corrosive, mobile ions oncethe finished chip is operating.Figure 1.3 presented a cross-sectional view of an MLM stack emphasizing the vertical layering of metal and dielectric, e.g., M I-ILD1-M2.Additional insight into PVD interconnect issues is provided by a plan view(Fig.
1.4) showing the metal wiring in a given layer with length L andcross-sectional, current-carrying area of T • W. The RC time-constantdelay introduced by this wiring scheme is then determined by (1) the resistance of the lines, R, (2) their pitch, P, which affects the lateral line-toline capacitance, C L, and (3) their vertical separation, which affects thelayer-to-layer capacitance, C v. Assuming the lines are very denselypacked, their pitch P might be, say, twice the metal line width (i.e., P =2W).
Also, the vertical thickness of dielectric above and below a metal lineR - 2pL/PTC - 2 (CL -I- C V )-2 ~ Eo (2L T/P + L P/2 T)R C - 2 (CL+ C V) - 2 p ~ ~o (4L2/p 2+ L2/T 2)FIG. 1.4 Simplified plan view of wiring in an IC indicating how the line resistance and parasitic capacitance between metal lines contributes to the overall RC delay time.R.
POWELL AND S. M. ROSSNAGELwill be close to the thickness of the line. With these assumptions, it isstraightforward to estimate the RC delay [1.5] as follows:R = 2pLPTC = 2 ( C L + Cv)=2e%(1.2)2LT + LP)P2T(1.3)so that,,{ 4L 2 L2 )RC = zpeeo~--~ +--~,(1.4)where e0 is the permittivity of free space, e (sometimes written as k) is thedielectric constant of the interlayer insulator, and p is the resistivity of themetal line.It should be noted that while these equations can be used to gain insightinto MLM issues, they are a highly simplified treatment of a mathematically complex problem. For example, the simple treatment used to obtainEq.
(1.3) assumes that the vertical capacitance C v between two lines is proportional to their planar area L • W ~ similar to the elementary treatmentof a semi-infinite, parallel plate capacitor with capacitor plate area - LWand dielectric thickness T. This result would be valid when W > > T.However, when W is comparable or less than T, a rigorous treatment of theproblem ~ which involves solving the second-order partial differentialLaplace's equation ~ shows that C v is proportional to log W and not to W.Hence, while narrowing the width of interconnect lines is expected to reduce interlayer capacitance, the gains will be much less than predicted byelementary theory once line width has been scaled down to the dielectricthickness, which today is ~ 1 /xm.Equation (1.4) shows that interconnect delay is directly proportional tothe product pc, which has driven the move toward higher-conductivityPVD metals (e.g., pure Cu with p = 1.7/xlI-cm versus AI-0.5%Cu withp = 3.0/xlI-cm) and/or lower dielectric constant insulators (e.g., fluorinecontaining CVD oxide with e ~ 3 versus conventional CVD oxide with~ 4).
Going to a lower dielectric constant insulator also reduces the ACpower consumed by the chip since this power loss is directly proportionalto e. The LZ-dependence in Eq. (1.4) shows the value of using multiple levels of wiring that reduce the line length per layer, with a quadratic reduction in RC time constant associated with that layer of wiring. On the otherhand, increased levels of metal wiring on a chip also require increased cap-INTRODUCTION9ital investment by the chip maker. Since the performance-driven trend inMLM materials away from A1/SiO 2 and toward Cu/low-k dielectrics willallow fewer levels of metal to be used for the same device generation, aconsiderable cost savings is expected as well. For example, it has been estimated by SEMATECH that $1.3B in back-end-of-line capital equipmentwill be required to build a 10,000-wafer-per-week fab producing a highend microprocessor (0.18 /xm) having eight levels of metal and A1/SiO 2wiring.
However, by switching to Cu/low-k dielectric wiring, the same device performance could be achieved using only five levels of metal. Thenet result of this simplified device architecture is that the capital equipment investment can be reduced by $500M.Figure 1.3 indicates that a variety of films are used to engineer a contact or via plug having appropriate electrical and mechanical propertiesfor the devices and circuits being fabricated. For example, a PVD "aluminum plug" might actuallev consist at the contact level of a thin bottomlayer of Ti ( ~ 5 nm = 50 A) to reduce contact resistance to the exposedSi (by chemically reducing native SiO 2 and also reacting to form a lowcontact resistance TiSi e film after annealing), a thin liner sleeve of TiN( ~ 10 nm = 100/~) to serve as a diffusion barrier between the A1 and theSi, and the actual thick plug of A1-0.5%Cu ( ~ 1 /zm). Similarly, a PVD"aluminum interconnect line" might actually consist of an engineered slabof several films (e.g., TiN/A1-0.5%Cu/Ti/TiN with the Ti/TiN on top),each chosen to enhance a desired property such as resistance to electromigration or to improve a subsequent process step such as a TiN antireflection coating (ARC), which is added to facilitate photoresist patterningwith optical lithography.As a practical matter, there are only two thickness ranges of interest forPVD films used in microelectronics.
Roughly speaking, they are 50-500 ]kfor contacts, barriers, liners, and ARC layers, and 0.5-1 /xm for contactplugs, via plugs, and interconnect lines. The ratio of height-to-width (i.e.,the aspect ratio, AR) of features to be coated or filled with metal can rangefrom zero for a planar surface to AR - 5"1 or even 10"1 for a contact holein advanced devices. A common practice is to use closely packed lowerlevels of metal for local interconnections and thicker, higher conductivity,wider pitched metal patterns at upper levels for power supply buses andglobal interconnections. Given more or less the same interlayer dielectricthickness between levels, the via holes at upper levels then tend to be lesssteep than those at lower levels; this facilitates step coverage or filling withPVD metal. This is reflected by the fact that although fabrication of an advanced IC (e.g., a microprocessor with minimum feature size of 0.25/zm)requires on the order of 25 lithographic mask levels, only 5 of these masksR.
POWELL AND S. M. ROSSNAGELwill contain features with dimension <- 0.35/zm. On the other hand, as willbe discussed in Chapter 5, the so-called thermal budget allowed for advanced chips leads to lower-temperature processing at the via levels thanat the contact level, making it harder to achieve this architectural benefit.Considering the fact that virtually any solid metallic or ceramic targetcan be sputtered, the number of materials sputter deposited in Si microelectronic fabrication is remarkably small - - and many of these serve useful dual purposes (e.g., a TiN ARC layer also helps harden the A1 interconnect slab against stress migration failure).
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