Roland A. - PVD for microelectronics (779636), страница 27
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During PVD itself, the deposition temperature can be used to controlsuch properties as film morphology, grain size and crystal orientation, andstress and step coverage (i.e., surface adatom mobility). Also, many advanced PVD processes m such as the two-step of AI planarization process(so-called cold-hot p r o c e s s ) m depend critically on control of wafer temperature both to deposit a suitable PVD Ti or TiN wetting layer prior toPVD AI and to provide a time-temperature profile during PVD AI thatminimizes void formation during the "cold" AI step and maximizes voidannihilation during the "hot" AI step.Thermal BudgetAlthough there are many process-driven reasons to control and/or reducewafer temperature in PVD, it is usually stated that PVD temperature mustcome down to meet a device-driven thermal budget that quantifies the totaltime at elevated temperature allowed to manufacture an advanced device.Actually, this statement can be misleading.
The thermal budget conceptwas introduced to address the thermal diffusion of dopants that are precisely introduced in semiconductor devices to delineate such things as theposition and depth of p-n junctions. The ability to form a junction that is138R. P O W E L L AND S. M. R O S S N A G E Lboth shallow and precisely controlled is at odds with excessive dopant diffusion. Simple one-dimensional diffusion theory shows that the distancediffused by a dopant in a time t is given by x ~ 2(Dt) 1/2, where the diffusion coefficient D depends exponentially on temperature T (viz., D = D oexp(Ea/kT)). This argues for keeping the temperature of a given processstep low or greatly reducing the time at elevated temperature as with arapid thermal anneal.
Also, since the total diffused distance is statisticallyadditive (Xtota I = ~ / X 2 -k- X 2 -t- 9 9 "), successive elevated temperature stepscan quickly use up the thermal budget set by the dimensions and dimensional tolerances of the device design.The problem in applying this dopant-related concept to PVD is thatPVD process steps rarely exceed 500~ and the total time at elevated temperature is usually less than a few minutes, so that dopant diffusion is negligible (e.g., the fast-diffusing p-type dopant B diffuses about 10 ~ incrystalline Si after 400 hours at 600~On the other hand, there are othercompelling reasons to reduce PVD time and/or temperature. Clearly, evena small reduction in time of a lengthy degas or reflow step could resultin measurably improved throughput. With regard to temperature, lowdielectric-constant (low-k) interlayer dielectrics are under active development to reduce on-chip RC time-constant signal delays in multilevel metallization.
Since many of the candidate materials are polymer-based andare degraded or destroyed by elevated temperature ( > 400~there is aneed to reduce maximum process temperatures during PVD to compatiblelevels and to reduce the time spent close to the temperature of degradation. Also, when a metal interconnect line is subjected to high-temperatureexcursions, a phenomenon known as stress voiding can occur. In this situation, voids are formed in the metal as the result of stress imposed by thethermal expansion mismatch with the underlying and overlying dielectricsand by the intrinsic stress and microstructure of the interconnect itself.Stress voiding can also accelerate failure due to electromigration.
Therefore the thermal budget for PVD really translates into a rather complexmaterials-dependent limit on process temperature and a wafer throughputdependent limit on process time.Temperature during PVDControl of wafer temperature has allowed PVD to be successfully appliedin advanced microelectronic applications and is often considered an enabling technology for PVD. For convenience we will focus on sputter deposition, although the basic physical arguments also will apply to othervacuum-processing steps associated with PVD such as degas and preclean.SPUTTERING TOOLS139Also, the mathematical treatment of wafer heating/cooling is intentionallysimplified to illustrate key aspects of the topic. For a more rigorous treatment, the reader is directed to refs. 5.25-5.27.Figure 5.24 illustrates the thermal environment of a wafer during PVD.The wafer is assumed to be held in close proximity to a substrate holderand is surrounded by grounded sputter shields.
Although a generalizedsubstrate heater is shown in Fig. 5.24, in the following discussion we donot consider active substrate heating. The principal thermal input to thewafer are then associated with irradiation, particle bombardment, and thermodynamic effects. Regarding the kinetic energy associated with particlebombardment, one should consider (1) incident-sputtered metal atoms, (2)bombardment by Ar § due to the wafer being more negative than theplasma, (3) bombardment by energetic neutralized Ar, and (4) bombardment by energetic electrons from the magnetron plasma that escape alongnon-reentrant field lines. Regarding thermodynamic effects, one shouldconsider (5) the heat of condensation, which is released when the depositing sputtered atoms go from the gaseous phase to the solid phase as theyadsorb onto the wafer surface and (6) the heat of neutralization, which isgiven up as Ar + ions combine with electrons at the wafer surface.
(7)Blackbody radiation emitted from either the plasma or from potentially hotFIG. 5.24Wafer thermal environment during PVD.140R. P O W E L L AND S. M. R O S S N A G E Lobjects m such as the target and sputter shields w can all be absorbed tosome extent by the wafer. (8) Finally, there is also the hot gas within thechamber, which can be at quite high temperatures ( > 400~While thethermal situation during DC magnetron sputtering is complex, it turns outfor many microelectronic applications that energetic atom and ion bombardment make up the majority of the heat input ( ~ 60-70%), with theheat of condensation accounting for the remainder.Regarding thermal output from the wafer, the possible mechanisms areconduction, convection, and/or radiation. At the low pressures used inPVD ( ~ 1-10 mTorr), convection is not relevant.
The thermal conductivity of gases at low pressure is so small (e.g., the heat transfer coefficientof Ar at 1 mTorr is ~ 10 -5 W/cm2-K) that gas-phase conductive heat lossis also negligible. Also, even though the wafer and substrate holder maybe in physical contact, the point nature of the contact on a microscopicscale greatly reduces the effective cross-sectional area through which heatcan flow, ruling out effective solid-phase conductive heat loss.
It is oftenbelieved that clamping a wafer more tightly against the substrate holderwill improve heat conduction, but this does little to increase the actual microscopic contact area. The result is that, unless intentional backside-gasassisted heat transfer is employed, radiation is the dominant heat lossmechanism.With these assumptions, the one-dimensional heat equation for the waferin Fig. 5.24 can be written asdTpC, z dt=(I~in -(~out(5.2)where p, C , and z are the density, specific heat, and thickness of Si, respectively. The density of Si is 2.33 gm/cm 3, and while C is a function oftemperature, a value of ~ 0.7 J/gm-K is a typical PVD temperature.
~in isthe incident energy flux, and ~out is the sum of the separate radiative heatlosses from the front and back faces of the wafer.We now consider the various mechanisms for heat gain and loss at thewafer, assuming for the moment that neither intentional wafer heating norcooling are being employed.1. Kinetic Energy of Sputtered Atoms. Sputtered-atom incident kineticenergy flux can be calculated using the Thompson energy distribution presented in Chapter 2.
However, as a first approximation we take the averageatom energy < E > for materials such as AI and Ti to be ~ 12 eV. Knowingthe incident deposition rate (e.g., 1 /~m/min of A1) and atomic density ofSPUTTERING TOOLS141the metal ( ~ 6 x 10 22 A1 atoms/cm 3) allows one to calculate the incidentsputter flux density J ( ~ 1017 A1 atoms/sec-cm2), leading to an incidentpower density given by the product of J x < E > ~ 1.2 x 1018 eV/seccm 2 = 0.2 W / c m 2.2. Kinetic Energy of Incident Ar Ions. For an electrically nonbiasedwafer, the plasma potential is in general ~ 10 V more positive than thewafer surface and Ar + bombardment of the wafer occurs with energy nottoo different than that of the incident metal atoms.
Experimental data forhigh-rate PVD AI suggests that the flux of Ar + at the wafer is ~ 2 0 - 3 0 %of the flux of A1 atoms [5.26].3. Kinetic Energy of Energetic Neutrals. An energetic, or "fast," neutralis an Ar ion that has been neutralized at the target surface and reflectedback toward the wafer. These atoms can have considerably higher energy(e.g., 50 eV = 600,000 K) than the Ar atoms in the process gas (e.g., 0.05eV ~ 600 K). Both the number and energy of these fast neutrals dependsstrongly on whether the mass of the incident Ar ion (m i = 40 amu) isgreater than or less than the mass of the target atoms (m,).
Figure 5.25shows a Monte Carlo calculation of fraction R of reflected, neutralized Ar ~and m a x i m u m reflected energy (E r) for l-keV Ar + bombardment of various mass targets. The two most commonly sputtered microelectronic materials are AI alloys and Ti or TiN. Since the mass of AI (m t = 27 amu) isless than that of Ar, we see from Fig. 5.25 that energenc neutral productionis insignificant. Also, even though the mass of Ti (m t = 48 amu) is greaterthan that of Ar, both the fraction of reflected Ar ( < 0.1%) and its m a x i m u menergy ( < 60 eV) suggest that they are not a significant source of waferheating. Whereas energetic neutrals should be considered for specific targets with ultrahigh mass such as Ti-W, we ignore their contribution in thisgeneral discussion of wafer heating.4.
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